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N. S. Nagaraj: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. N. S. Nagaraj, Poras T. Balsara, Cyrus Cantrell
    Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:141- [Conf]
  2. N. S. Nagaraj
    A New Optimizer for Performance Optimization of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:148-153 [Conf]
  3. N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill
    BEOL variability and impact on RC extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:758-759 [Conf]
  4. N. S. Nagaraj, Frank Cano, Haldun Haznedar, Duane Young
    A Practical Approach to Static Signal Electromigration Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:572-577 [Conf]
  5. N. S. Nagaraj, Kenneth L. Shepard, Takahide Inone
    Taming Noise in Deep Submicron Digital Integrated Circuits (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:100-101 [Conf]
  6. N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang
    When bad things happen to good chips (panel session). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:736-737 [Conf]
  7. Renuka Sindhgatta, Swaminathan Natarajan, Krishnakumar Pooloth, Colin Pinto, N. S. Nagaraj
    Autonomic Incident Manager for Enterprise Applications. [Citation Graph (0, 0)][DBLP]
    GCC Workshops, 2004, pp:642-649 [Conf]
  8. N. S. Nagaraj
    A New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2102-2105 [Conf]
  9. N. S. Nagaraj, Paul Krivacek, Mark Harward
    Approximate Computation of Signal Characteristics of On-chip RC Interconnect Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:109-112 [Conf]
  10. R. G. Bushroe, S. DasGupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele
    Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:212-217 [Conf]
  11. Narain Arora, N. S. Nagaraj
    Interconnect Modeling for Timing, Signal Integrity and Reliability. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:13- [Conf]
  12. Wonjae L. Kang, Brad Potts, Ray Hokinson, John Riley, David Doman, Frank Cano, N. S. Nagaraj, Noel Durrant
    Enabling DIR(Designing-In-Reliability) through CAD Capabilities. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:151-156 [Conf]
  13. N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus Cantrell
    Benchmarks for Interconnect Parasitic Resistance and Capacitance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:163-0 [Conf]
  14. Usha Narasimha, Binu Abraham, N. S. Nagaraj
    Statistical Analysis of Capacitance Coupling Effects on Delay and Noise. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:795-800 [Conf]
  15. Steffen Rochel, N. S. Nagaraj
    Full-Chip Signal Interconnect Analysis for Electromigration Reliability. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:337-340 [Conf]
  16. N. S. Nagaraj
    Dealing with interconnect process variations. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:39- [Conf]
  17. Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich
    A 800 MHz System-on-Chip for Wireless Infrastructure Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:381-0 [Conf]
  18. N. S. Nagaraj
    Interconnect Process Variations: Theory and Practice. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:11- [Conf]
  19. N. S. Nagaraj, Poras T. Balsara, Cyrus Cantrell
    Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:141- [Conf]
  20. N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara
    Interconnect Modeling for Copper/Low-k Technologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:425-0 [Conf]
  21. N. S. Nagaraj, Frank Cano, Duane Young, Deepak Vohra, Manoj Das
    A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:370-375 [Conf]
  22. N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus Cantrell
    The Impact of Inductance on Transients Affecting Gate Oxide Reliability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:709-713 [Conf]
  23. Usha Narasimha, Anthony M. Hill, N. S. Nagaraj
    SmartExtract: Accurate Capacitance Extraction for SOC Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:786-789 [Conf]

  24. DFM in practice: hit or hype? [Citation Graph (, )][DBLP]


  25. Moore's Law: another casualty of the financial meltdown? [Citation Graph (, )][DBLP]


  26. Optimizing Interconnect for Performance in Standard Cell Library. [Citation Graph (, )][DBLP]


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