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Prabhat Mishra: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Prabhat Mishra, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama
    Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:458-466 [Conf]
  2. Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt
    An efficient retargetable framework for instruction-set simulation. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:13-18 [Conf]
  3. Mehrdad Reshadi, Prabhat Mishra
    Memory access optimizations in instruction-set simulators. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:237-242 [Conf]
  4. Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt
    Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:758-763 [Conf]
  5. Heon-Mo Koo, Prabhat Mishra
    Functional test generation using property decompositions for validation of pipelined processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1240-1245 [Conf]
  6. Prabhat Mishra, Nikil Dutt
    Graph-Based Functional Test Program Generation for Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:182-187 [Conf]
  7. Prabhat Mishra, Nikil D. Dutt
    Functional Coverage Driven Test Generation for Validation of Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:678-683 [Conf]
  8. Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama
    Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:36-43 [Conf]
  9. Prabhat Mishra, Nikil D. Dutt
    Functional Validation of Programmable Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:12-19 [Conf]
  10. Heon-Mo Koo, Prabhat Mishra
    Test generation using SAT-based bounded model checking for validation of pipelined processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:362-365 [Conf]
  11. Seok-Won Seong, Prabhat Mishra
    A bitmask-based code compression technique for embedded systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:251-254 [Conf]
  12. Prabhat Mishra, Nikil D. Dutt
    Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions. [Citation Graph (0, 0)][DBLP]
    DIPES, 2002, pp:81-90 [Conf]
  13. Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau
    Functional abstraction driven design space exploration of heterogeneous programmable architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:256-261 [Conf]
  14. Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir
    Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:33-36 [Conf]
  15. Prabhat Mishra, Nikil D. Dutt
    A Methodology for Validation of Microprocessors using Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:83-88 [Conf]
  16. Prabhat Mishra, Nikil D. Dutt, Yaron Kashai
    Functional Verification of Pipelined Processors: A Case Study. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:79-84 [Conf]
  17. Prabhat Mishra, Heon-Mo Koo, Zhuo Huang
    Language-driven Validation of Pipelined Processors using Satisfiability Solvers. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:119-126 [Conf]
  18. Prabhat Mishra, Arun Kejariwal, Nikil Dutt
    Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:226-232 [Conf]
  19. Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau
    Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:70-75 [Conf]
  20. Prabhat Mishra, Arun Kejariwal, Nikil Dutt
    Synthesis-driven Exploration of Pipelined Embedded Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:921-926 [Conf]
  21. Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau
    Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:458-0 [Conf]
  22. Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir
    A Top-Down Methodology for Microprocessor Validation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:122-131 [Journal]
  23. Mehrdad Reshadi, Nikil Dutt, Prabhat Mishra
    A retargetable framework for instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:431-452 [Journal]
  24. Prabhat Mishra, Nikil Dutt
    Modeling and validation of pipeline specifications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:1, pp:114-139 [Journal]
  25. Prabhat Mishra, Mahesh Mamidipaka, Nikil Dutt
    Processor-memory coexploration using an architecture description language. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:1, pp:140-162 [Journal]
  26. Prabhat Mishra, Aviral Shrivastava, Nikil Dutt
    Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:626-658 [Journal]
  27. Seok-Won Seong, Prabhat Mishra
    An efficient code compression technique using application-aware bitmask and dictionary selection methods. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:582-587 [Conf]

  28. A Retargetable Software Timing Analyzer Using Architecture Description Language. [Citation Graph (, )][DBLP]


  29. Specification-based compaction of directed tests for functional validation of pipelined processors. [Citation Graph (, )][DBLP]


  30. Generating test programs to cover pipeline interactions. [Citation Graph (, )][DBLP]


  31. PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme. [Citation Graph (, )][DBLP]


  32. Efficient decision ordering techniques for SAT-based test generation. [Citation Graph (, )][DBLP]


  33. Coverage-driven automatic test generation for uml activity diagrams. [Citation Graph (, )][DBLP]


  34. A novel test-data compression technique using application-aware bitmask and dictionary selection methods. [Citation Graph (, )][DBLP]


  35. Bitmask-based control word compression for NISC architectures. [Citation Graph (, )][DBLP]


  36. Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach. [Citation Graph (, )][DBLP]


  37. Efficient Placement of Compressed Code for Parallel Decompression. [Citation Graph (, )][DBLP]


  38. SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. [Citation Graph (, )][DBLP]


  39. Efficient Techniques for Directed Test Generation Using Incremental Satisfiability. [Citation Graph (, )][DBLP]


  40. Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems. [Citation Graph (, )][DBLP]


  41. Synchronized Generation of Directed Tests Using Satisfiability Solving. [Citation Graph (, )][DBLP]


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