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Publications of Author

1. Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
   A dynamically reconfigurable hardware-based cipher chip. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2001, pp:11-12 [Conf]
   
2. Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Y. Meng
   FeRAM Circuit Technology for System on a Chip. [Citation Graph (0, 0)][DBLP]
   Evolvable Hardware, 1999, pp:193-0 [Conf]
   
3. Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
   VLSI architecture of dynamically reconfigurable hardware-based cipher. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2001, pp:734-737 [Conf]
   
4. 
   Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. [Citation Graph (, )][DBLP]
   
   
5. 
   Coarse-grained dynamically reconfigurable architecture with flexible reliability. [Citation Graph (, )][DBLP]
   
   
6. 
   Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --. [Citation Graph (, )][DBLP]
   
   
7. 
   Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. [Citation Graph (, )][DBLP]
   
   
8. 
   Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. [Citation Graph (, )][DBLP]
   
   
9. 
   Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. [Citation Graph (, )][DBLP]
   
   
10. 
    Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. [Citation Graph (, )][DBLP]