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Publications of Author

1. Gaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee
   Automatic extraction of function bodies from software binaries. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:928-931 [Conf]
   
2. Gaurav Mittal, Sreela Sasi
   Robust Preprocessing Algorithm for Face Recognition. [Citation Graph (0, 0)][DBLP]
   CRV, 2006, pp:57- [Conf]
   
3. Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee
   Automatic translation of software binaries onto FPGAs. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:389-394 [Conf]
   
4. David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee
   Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. [Citation Graph (0, 0)][DBLP]
   FCCM, 2004, pp:37-46 [Conf]
   
5. David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee
   Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2004, pp:397-400 [Conf]
   
6. David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee
   Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:595-601 [Conf]
   
7. David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee
   Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code. [Citation Graph (0, 0)][DBLP]
   LCPC, 2005, pp:76-90 [Conf]
   
8. David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee
   Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:465-468 [Conf]
   
9. Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee
   An Overview of a Compiler for Mapping Software Binaries to Hardware. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1177-1190 [Journal]
   
10. 
    An Efficient Video Enhancement Method Using LA*B* Analysis. [Citation Graph (, )][DBLP]
    
    
11. 
    Streaming implementation of a sequential decompression algorithm on an FPGA. [Citation Graph (, )][DBLP]
    
    
12. 
    A software pipelining algorithm in high-level synthesis for FPGA architectures. [Citation Graph (, )][DBLP]