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Jon T. Butler: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
    Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:378-383 [Conf]
  2. Tsutomu Sasao, Jon T. Butler
    On the minimization of SOPs for bi-decomposition functions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:219-224 [Conf]
  3. Tsutomu Sasao, Jon T. Butler
    A fast method to derive minimum SOPs for decomposable functions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:585-590 [Conf]
  4. Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
    Programmable Numerical Function Generators: Architectures and Synthesis Method. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:118-123 [Conf]
  5. Jon T. Butler, Tsutomu Sasao
    Multiple-Valued Combinational Circuits with Feedback. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:342-347 [Conf]
  6. Susan W. Butler, Jon T. Butler
    Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:372-379 [Conf]
  7. Jon T. Butler, Hans G. Kerkhoff, Siep Onneweer
    A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:286-291 [Conf]
  8. Jon T. Butler, J. L. Nowlin, Tsutomu Sasao
    Planarity in ROMDD's of Multiple-Valued Symmetric Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:236-241 [Conf]
  9. Jon T. Butler, Tsutomu Sasao
    On the Average Path Length in Decision Diagrams of Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:383-390 [Conf]
  10. Jon T. Butler, Kriss A. Schueller
    Worst Case Number of Terms in Symmetric Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:94-101 [Conf]
  11. Jon T. Butler, Tsutomu Sasao
    On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:83-88 [Conf]
  12. Young-hoon Chang, Jon T. Butler
    The Design of Current Mode CMOS Multiple-Valued Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:130-138 [Conf]
  13. Gerhard W. Dueck, Jon T. Butler
    Multiple-Valued Logic Operations with Universal Literals. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:73-79 [Conf]
  14. Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler
    Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:66-74 [Conf]
  15. Tsutomu Sasao, Jon T. Butler
    Implementation of Multiple-Valued CAM Functions by LUT Cascades. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:11- [Conf]
  16. Tsutomu Sasao, Jon T. Butler
    Planar Multiple-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:28-35 [Conf]
  17. Tsutomu Sasao, Jon T. Butler
    A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:248-254 [Conf]
  18. Tsutomu Sasao, Jon T. Butler
    Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:55-60 [Conf]
  19. Tsutomu Sasao, Jon T. Butler
    A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:97-106 [Conf]
  20. Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko
    Experiments on FPRM Expressions for Partially Symmetric Logic Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:141-146 [Conf]
  21. Cem Yildirim, Jon T. Butler, Chyan Yang
    Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:17-23 [Conf]
  22. John M. Yurchak, Jon T. Butler
    HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:144-152 [Conf]
  23. Jon T. Butler
    Multiple-Valued Logic - Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1988, v:21, n:4, pp:13-15 [Journal]
  24. Jon T. Butler, Hans G. Kerkhoff
    Multiple-Valued CCD Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1988, v:21, n:4, pp:58-69 [Journal]
  25. Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko
    On the number of generators for transeunt triangles. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 2001, v:108, n:3, pp:309-316 [Journal]
  26. Jon T. Butler
    A Note on Cellular Automata Simulations [Citation Graph (0, 0)][DBLP]
    Information and Control, 1974, v:26, n:3, pp:286-295 [Journal]
  27. Jon T. Butler
    Synthesis of One-Dimensional Binary Cellular Automata Systems from Composite Local Maps [Citation Graph (0, 0)][DBLP]
    Information and Control, 1979, v:43, n:3, pp:304-326 [Journal]
  28. Patrick E. White, Jon T. Butler
    Synthesis of One-Dimensional Binary Scope-2 Flexible Cellular Systems from Initial Final Configuration Pairs [Citation Graph (0, 0)][DBLP]
    Information and Control, 1980, v:46, n:3, pp:241-256 [Journal]
  29. Jon T. Butler
    On the relationship between propagating context-dependent lindenmayer systems and cellular automata systems. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1982, v:28, n:1, pp:63-67 [Journal]
  30. Edward A. Bender, Jon T. Butler
    Enumeration of Structured Flowcharts [Citation Graph (0, 0)][DBLP]
    J. ACM, 1985, v:32, n:3, pp:537-548 [Journal]
  31. Jon T. Butler
    Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1978, v:25, n:3, pp:481-498 [Journal]
  32. Jon T. Butler
    Decomposable Maps in General Tessellation Structures. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 1979, v:18, n:1, pp:1-7 [Journal]
  33. Edward A. Bender, Jon T. Butler
    Asymptotic Aproximations for the Number of Fanout-Free Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:12, pp:1180-1183 [Journal]
  34. Edward A. Bender, Jon T. Butler
    On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:1, pp:82-98 [Journal]
  35. Jon T. Butler
    On the Number of Functions Realized by Cascades and Disjunctive Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:7, pp:681-690 [Journal]
  36. Jon T. Butler
    Restricted Cellular Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:11, pp:1139-1142 [Journal]
  37. Jon T. Butler
    Tandem Networks of Universal Cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:9, pp:785-799 [Journal]
  38. Jon T. Butler
    Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:8, pp:590-596 [Journal]
  39. Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III
    Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:4, pp:491-494 [Journal]
  40. Jon T. Butler, Kriss A. Schueller
    On the Equivalence of Cost Functions in the Design of Circuits by Costtable. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:6, pp:842-844 [Journal]
  41. Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura
    Average Path Length of Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:9, pp:1041-1053 [Journal]
  42. Joo-Kang Lee, Jon T. Butler
    A Characterization of t/s-Diagnosability an Sequential t-Diagnosability in Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:10, pp:1298-1304 [Journal]
  43. Tsutomu Sasao, Jon T. Butler
    Worst and Best Irredundant Sum-of-Products Expressions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:9, pp:935-948 [Journal]
  44. Kriss A. Schueller, Jon T. Butler
    Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:2, pp:205-209 [Journal]
  45. Kriss A. Schueller, Jon T. Butler
    On the Design of Cost-Tables for Realizing Multiple-Valued Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:2, pp:178-189 [Journal]
  46. Parthasarathy P. Tirumalai, Jon T. Butler
    Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:2, pp:167-177 [Journal]
  47. Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
    Numerical Function Generators Using LUT Cascades. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:6, pp:826-838 [Journal]
  48. Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich
    Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1386-1388 [Journal]
  49. Hui Qin, Tsutomu Sasao, Jon T. Butler
    Implementation of LPM Address Generators on FPGAs. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:170-181 [Conf]

  50. Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. [Citation Graph (, )][DBLP]


  51. Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. [Citation Graph (, )][DBLP]


  52. Programmable Numerical Function Generators for Two-Variable Functions. [Citation Graph (, )][DBLP]


  53. Numerical function generators using bilinear interpolation. [Citation Graph (, )][DBLP]


  54. Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions. [Citation Graph (, )][DBLP]


  55. A Quaternary Decision Diagram Machine and the Optimization of its Code. [Citation Graph (, )][DBLP]


  56. Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs. [Citation Graph (, )][DBLP]


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