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Rohini Krishnan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan
    A New Divide and Conquer Method for Achieving High Speed Division in Hardware. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:535-540 [Conf]
  2. Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek
    Energy-efficient FPGA interconnect design. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:42-47 [Conf]
  3. Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
    Low energy FPGA interconnect design. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:255- [Conf]
  4. Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume
    Energy-efficient FPGA interconnect architecture design (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:268- [Conf]
  5. Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick
    Encoded-Low Swing Technique for Ultra Low Power Interconnect. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:240-251 [Conf]
  6. Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
    Low energy FPGA interconnect design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:393-396 [Conf]
  7. Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar
    Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:177-182 [Conf]
  8. Rohini Krishnan, José Pineda de Gyvez
    Low Energy Switch Block For FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:209-214 [Conf]
  9. Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan
    A New Divide and Conquer Method for Achieving High Speed Division in Hardware. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:535-540 [Conf]

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