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Srinath R. Naidu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Srinath R. Naidu
    Timing Yield Calculation Using an Impulse-train Approach. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:219-224 [Conf]
  2. Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
    Statistical timing for parametric yield prediction of digital integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:932-937 [Conf]
  3. Srinath R. Naidu, E. T. A. F. Jacobs
    Minimizing stand-by leakage power in static CMOS circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:370-376 [Conf]
  4. Srinath R. Naidu
    Timing Yield Calculation Using an Impulse-Train Approach. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:219-224 [Conf]
  5. Srinath R. Naidu
    Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:265-270 [Conf]
  6. Srinath R. Naidu, Vijay Chandru
    On Synthesis of Easily Testable (k, K) Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:11, pp:1490-1494 [Journal]
  7. Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
    Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2376-2392 [Journal]

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