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Publications of Author

1. Massoud Pedram, Xunwei Wu
   Analysis of power-clocked CMOS with application to the design of energy-recovery circuits. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:339-344 [Conf]
   
2. Massoud Pedram, Qing Wu, Xunwei Wu
   A New Design for Double Edge Triggered Flip-flops. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1998, pp:417-421 [Conf]
   
3. Xunwei Wu, Jian Wei, Massoud Pedram, Qing Wu
   Low-power design of sequential circuits using a quasi-synchronous derived clock. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:345-350 [Conf]
   
4. Rakesh Mehrotra, Massoud Pedram, Xunwei Wu
   Comparison between nMos Pass Transistor logic style vs. CMOS Complementary Cells. [Citation Graph (0, 0)][DBLP]
   ICCD, 1997, pp:130-135 [Conf]
   
5. Xunwei Wu, Massoud Pedram
   Low power sequential circuit design by using priority encoding and clock gating. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2000, pp:143-148 [Conf]
   
6. Xunwei Wu
   The Theory of Clipping Voltage-Switches and Design of Quaternary nMOS Circuits. [Citation Graph (0, 0)][DBLP]
   ISMVL, 1992, pp:119-125 [Conf]
   
7. Xunwei Wu, Xiaowei Deng
   Theory of Grounded Current Switches and Quatemary IIL Circuits. [Citation Graph (0, 0)][DBLP]
   ISMVL, 1991, pp:210-215 [Conf]
   
8. Xunwei Wu, Massoud Pedram
   Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2000, pp:453-459 [Conf]
   
9. Xunwei Wu, Xuanchang Zhou
   Novel ?-Type Resistor Network in D/A Converter Based on Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2000, pp:227-0 [Conf]
   
10. Xunwei Wu, Massoud Pedram
    Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:209-214 [Conf]
    
11. Shoujue Wang, Xunwei Wu, Hongjuan Feng
    The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:178-181 [Conf]
    
12. Xunwei Wu, Xiexiong Chen, Jizhong Shen
    Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:222-227 [Conf]
    
13. Yinshui Xia, Xunwei Wu, Penjung Wang
    Design of Ternary Schmitt Triggers Based on Its Sequential Characteristics. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:156-160 [Conf]
    
14. Yinshui Xia, Xunwei Wu, A. E. A. Almaini
    Power Minimization of FPRM Functions Based on Polarity Conversion. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:3, pp:325-331 [Journal]