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Sani R. Nassif: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sani R. Nassif
    Modeling and forecasting of manufacturing variations (embedded tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:145-150 [Conf]
  2. Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori
    Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:267-268 [Conf]
  3. Kanak Agarwal, Sani R. Nassif
    Statistical analysis of SRAM cell stability. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:57-62 [Conf]
  4. Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula
    Variational delay metrics for interconnect timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:381-384 [Conf]
  5. Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
    Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:69-72 [Conf]
  6. Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas
    Impact of interconnect variations on the clock skew of a gigahertz microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:168-171 [Conf]
  7. Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha Chandrakasan, Rakesh Vallishayee, Sani R. Nassif
    A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:172-175 [Conf]
  8. N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang
    When bad things happen to good chips (panel session). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:736-737 [Conf]
  9. Sani R. Nassif, Joseph N. Kozhaya
    Fast power grid simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:156-161 [Conf]
  10. Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic
    Variation-aware analysis: savior of the nanometer era? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:411-412 [Conf]
  11. Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse
    The Titanic: what went wrong! [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:349-350 [Conf]
  12. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
    Random walks in a supply network. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:93-98 [Conf]
  13. Haihua Su, Emrah Acar, Sani R. Nassif
    Power grid reduction based on algebraic multigrid principles. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:109-112 [Conf]
  14. Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
    Congestion-driven codesign of power and signal networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:64-69 [Conf]
  15. Luís M. Vidigal, Sani R. Nassif, Stephen W. Director
    CINNAMON: coupled integration and nodal analysis of MOS networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:179-185 [Conf]
  16. Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi
    A Linear-Centric Simulation Framework for Parametric Fluctuations. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:568-575 [Conf]
  17. Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
    Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:958-963 [Conf]
  18. Sani R. Nassif
    Designing Closer to the Edge. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:636-0 [Conf]
  19. Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob Abraham
    Estimating path delay distribution considering coupling noise. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:61-66 [Conf]
  20. Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
    Multigrid-Like Technique for Power Grid Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:480-487 [Conf]
  21. Sani R. Nassif, Duane S. Boning, Nagib Hakim
    The care and feeding of your statistical static timer. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:138-139 [Conf]
  22. Sani R. Nassif, Tuyen V. Nguyen
    SOI technology and tools (abstract). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:459- [Conf]
  23. Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar
    A chip-level electrostatic discharge simulation strategy. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:315-318 [Conf]
  24. Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
    An accurate sparse matrix based framework for statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:231-236 [Conf]
  25. Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky
    Analytical modeling of SRAM dynamic stability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:315-322 [Conf]
  26. Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif
    Benefits and Costs of Power-Gating Technique. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:559-566 [Conf]
  27. Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
    Power-aware global signaling strategies. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:604-607 [Conf]
  28. Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long
    Static timing analysis based circuit-limited-yield estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:81-84 [Conf]
  29. Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
    Leakage and leakage sensitivity computation for combinational circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:96-99 [Conf]
  30. Sani R. Nassif
    The impact of variability on power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:350- [Conf]
  31. Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif
    Approaches to run-time and standby mode leakage reduction in global buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:188-193 [Conf]
  32. Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif
    Full chip leakage estimation considering power supply and temperature variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:78-83 [Conf]
  33. Sani R. Nassif
    Model to hardware matching: for nano-meter scale technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:203-206 [Conf]
  34. David P. LaPotin, Uttam Ghoshal, Eli Chiprout, Sani R. Nassif
    Physical design challenges for performance. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:225-226 [Conf]
  35. Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif
    An efficient surface-based low-power buffer insertion algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:86-93 [Conf]
  36. Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
    An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:68-73 [Conf]
  37. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
    Early-stage power grid analysis for uncertain working modes. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:132-137 [Conf]
  38. Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi
    Time-Domain Simulation of Variational Interconnect Models. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:419-424 [Conf]
  39. Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu
    Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:431-436 [Conf]
  40. Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif
    SRAM Local Bit Line Access Failure Analyses. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:204-209 [Conf]
  41. Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long
    Timing Yield Estimation from Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:437-442 [Conf]
  42. Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida N. Kanj, Sani R. Nassif
    System-Level SRAM Yield Enhancement. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:179-184 [Conf]
  43. Sani R. Nassif
    Design for Variability in DSM Technologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:451-454 [Conf]
  44. Sani R. Nassif, Zhuo Li
    A More Effective CEFF. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:648-653 [Conf]
  45. Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif
    Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:644-649 [Conf]
  46. Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif
    Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:33-40 [Conf]
  47. Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif
    Optimal shielding/spacing metrics for low power design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:167-172 [Conf]
  48. Juan Antonio Carballo, Sani R. Nassif
    Impact of Technology in Power-Grid-Induced Noise. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:45-54 [Conf]
  49. Sani R. Nassif, Onsi Fakhouri
    Technology trends in power-grid-induced noise. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:55-59 [Conf]
  50. Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu
    Test structures for delay variability. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:109- [Conf]
  51. Anirudh Devgan, Sani R. Nassif
    Power Variability and Its Impact on Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:679-682 [Conf]
  52. Juan Antonio Carballo, Sani R. Nassif
    Impact of Design-Manufacturing Interface on SoC Design Methodologies. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:183-191 [Journal]
  53. Sani R. Nassif, Soha Hassoun
    Guest Editors' Introduction: On-Chip Power Distribution Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:5-6 [Journal]
  54. Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
    A multigrid-like technique for power grid analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1148-1160 [Journal]
  55. Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
    FABRICS II: A Statistically Based IC Fabrication Process Simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:1, pp:40-46 [Journal]
  56. Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
    A Methodology for Worst-Case Analysis of Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:104-113 [Journal]
  57. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
    Early-stage power grid analysis for uncertain working modes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:676-682 [Journal]
  58. Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
    Power grid analysis using random walks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1204-1224 [Journal]
  59. Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
    A methodology for the simultaneous design of supply and signal networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1614-1624 [Journal]
  60. Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
    Optimal decoupling capacitor sizing and placement for standard-cell layout designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:428-436 [Journal]
  61. Ritu Singhal, Asha Balijepalli, Anupama Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao
    Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:823-828 [Conf]
  62. Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
    Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:148-153 [Conf]
  63. Kanak Agarwal, Sani R. Nassif
    Characterizing Process Variation in Nanometer CMOS. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:396-399 [Conf]
  64. Emrah Acar, Kanak Agarwal, Sani R. Nassif
    Characterization of total chip leakage using inverse (reciprocal) gamma distribution. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  65. Sani R. Nassif, Kanak Agarwal, Emrah Acar
    Methods for estimating decoupling capacitance of nonswitching circuit blocks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  66. Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
    Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  67. Emrah Acar, Anirudh Devgan, Sani R. Nassif
    Leakage and Leakage Sensitivity Computation for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:172-181 [Journal]

  68. Technology modeling and characterization beyond the 45nm node. [Citation Graph (, )][DBLP]


  69. Power grid analysis benchmarks. [Citation Graph (, )][DBLP]


  70. Analytical model for the impact of multiple input switching noise on timing. [Citation Graph (, )][DBLP]


  71. Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. [Citation Graph (, )][DBLP]


  72. Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level. [Citation Graph (, )][DBLP]


  73. Analyzing the impact of process variations on parametric measurements: Novel models and applications. [Citation Graph (, )][DBLP]


  74. A resilience roadmap. [Citation Graph (, )][DBLP]


  75. A methodology for propagating design tolerances to shape tolerances for use in manufacturing. [Citation Graph (, )][DBLP]


  76. MAPS: multi-algorithm parallel circuit simulation. [Citation Graph (, )][DBLP]


  77. Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]


  78. Simultaneous layout migration and decomposition for double patterning technology. [Citation Graph (, )][DBLP]


  79. An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. [Citation Graph (, )][DBLP]


  80. SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. [Citation Graph (, )][DBLP]


  81. Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. [Citation Graph (, )][DBLP]


  82. Physical design challenges beyond the 22nm node. [Citation Graph (, )][DBLP]


  83. Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. [Citation Graph (, )][DBLP]


  84. A Root-Finding Method for Assessing SRAM Stability. [Citation Graph (, )][DBLP]


  85. A Design Model for Random Process Variability. [Citation Graph (, )][DBLP]


  86. Statistical yield analysis of silicon-on-insulator embedded DRAM. [Citation Graph (, )][DBLP]


  87. The impact of BEOL lithography effects on the SRAM cell performance and yield. [Citation Graph (, )][DBLP]


  88. Model to Hardware Matching for nm Scale Technologies. [Citation Graph (, )][DBLP]


  89. Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips. [Citation Graph (, )][DBLP]


  90. Guest Editors' Introduction: Process Variation and Stochastic Design and Test. [Citation Graph (, )][DBLP]


  91. 'Tis the gift to be simple. [Citation Graph (, )][DBLP]


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