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## Search the dblp DataBase
Sani R. Nassif:
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## Publications of Author- Sani R. Nassif
**Modeling and forecasting of manufacturing variations (embedded tutorial).**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:145-150 [Conf] - Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori
**Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2001, pp:267-268 [Conf] - Kanak Agarwal, Sani R. Nassif
**Statistical analysis of SRAM cell stability.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:57-62 [Conf] - Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula
**Variational delay metrics for interconnect timing analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:381-384 [Conf] - Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
**Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:69-72 [Conf] - Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas
**Impact of interconnect variations on the clock skew of a gigahertz microprocessor.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:168-171 [Conf] - Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha Chandrakasan, Rakesh Vallishayee, Sani R. Nassif
**A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:172-175 [Conf] - N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang
**When bad things happen to good chips (panel session).**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:736-737 [Conf] - Sani R. Nassif, Joseph N. Kozhaya
**Fast power grid simulation.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:156-161 [Conf] - Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic
**Variation-aware analysis: savior of the nanometer era?**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:411-412 [Conf] - Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse
**The Titanic: what went wrong!**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:349-350 [Conf] - Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
**Random walks in a supply network.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:93-98 [Conf] - Haihua Su, Emrah Acar, Sani R. Nassif
**Power grid reduction based on algebraic multigrid principles.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:109-112 [Conf] - Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
**Congestion-driven codesign of power and signal networks.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:64-69 [Conf] - Luís M. Vidigal, Sani R. Nassif, Stephen W. Director
**CINNAMON: coupled integration and nodal analysis of MOS networks.**[Citation Graph (0, 0)][DBLP] DAC, 1986, pp:179-185 [Conf] - Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi
**A Linear-Centric Simulation Framework for Parametric Fluctuations.**[Citation Graph (0, 0)][DBLP] DATE, 2002, pp:568-575 [Conf] - Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
**Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:958-963 [Conf] - Sani R. Nassif
**Designing Closer to the Edge.**[Citation Graph (0, 0)][DBLP] DATE, 2000, pp:636-0 [Conf] - Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob Abraham
**Estimating path delay distribution considering coupling noise.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2007, pp:61-66 [Conf] - Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
**Multigrid-Like Technique for Power Grid Analysis.**[Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:480-487 [Conf] - Sani R. Nassif, Duane S. Boning, Nagib Hakim
**The care and feeding of your statistical static timer.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:138-139 [Conf] - Sani R. Nassif, Tuyen V. Nguyen
**SOI technology and tools (abstract).**[Citation Graph (0, 0)][DBLP] ICCAD, 1999, pp:459- [Conf] - Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar
**A chip-level electrostatic discharge simulation strategy.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:315-318 [Conf] - Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
**An accurate sparse matrix based framework for statistical static timing analysis.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:231-236 [Conf] - Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky
**Analytical modeling of SRAM dynamic stability.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:315-322 [Conf] - Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif
**Benefits and Costs of Power-Gating Technique.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:559-566 [Conf] - Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
**Power-aware global signaling strategies.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2005, pp:604-607 [Conf] - Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long
**Static timing analysis based circuit-limited-yield estimation.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2002, pp:81-84 [Conf] - Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
**Leakage and leakage sensitivity computation for combinational circuits.**[Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:96-99 [Conf] - Sani R. Nassif
**The impact of variability on power.**[Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:350- [Conf] - Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif
**Approaches to run-time and standby mode leakage reduction in global buses.**[Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:188-193 [Conf] - Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif
**Full chip leakage estimation considering power supply and temperature variations.**[Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:78-83 [Conf] - Sani R. Nassif
**Model to hardware matching: for nano-meter scale technologies.**[Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:203-206 [Conf] - David P. LaPotin, Uttam Ghoshal, Eli Chiprout, Sani R. Nassif
**Physical design challenges for performance.**[Citation Graph (0, 0)][DBLP] ISPD, 1997, pp:225-226 [Conf] - Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif
**An efficient surface-based low-power buffer insertion algorithm.**[Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:86-93 [Conf] - Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
**An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.**[Citation Graph (0, 0)][DBLP] ISPD, 2002, pp:68-73 [Conf] - Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
**Early-stage power grid analysis for uncertain working modes.**[Citation Graph (0, 0)][DBLP] ISPD, 2004, pp:132-137 [Conf] - Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi
**Time-Domain Simulation of Variational Interconnect Models.**[Citation Graph (0, 0)][DBLP] ISQED, 2002, pp:419-424 [Conf] - Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu
**Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:431-436 [Conf] - Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif
**SRAM Local Bit Line Access Failure Analyses.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:204-209 [Conf] - Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long
**Timing Yield Estimation from Static Timing Analysis.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:437-442 [Conf] - Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida N. Kanj, Sani R. Nassif
**System-Level SRAM Yield Enhancement.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:179-184 [Conf] - Sani R. Nassif
**Design for Variability in DSM Technologies.**[Citation Graph (0, 0)][DBLP] ISQED, 2000, pp:451-454 [Conf] - Sani R. Nassif, Zhuo Li
**A More Effective C**[Citation Graph (0, 0)][DBLP]_{EFF}. ISQED, 2005, pp:648-653 [Conf] - Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif
**Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:644-649 [Conf] - Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif
**Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.**[Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:33-40 [Conf] - Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif
**Optimal shielding/spacing metrics for low power design.**[Citation Graph (0, 0)][DBLP] ISVLSI, 2003, pp:167-172 [Conf] - Juan Antonio Carballo, Sani R. Nassif
**Impact of Technology in Power-Grid-Induced Noise.**[Citation Graph (0, 0)][DBLP] PATMOS, 2002, pp:45-54 [Conf] - Sani R. Nassif, Onsi Fakhouri
**Technology trends in power-grid-induced noise.**[Citation Graph (0, 0)][DBLP] SLIP, 2002, pp:55-59 [Conf] - Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu
**Test structures for delay variability.**[Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:109- [Conf] - Anirudh Devgan, Sani R. Nassif
**Power Variability and Its Impact on Design.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:679-682 [Conf] - Juan Antonio Carballo, Sani R. Nassif
**Impact of Design-Manufacturing Interface on SoC Design Methodologies.**[Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2004, v:21, n:3, pp:183-191 [Journal] - Sani R. Nassif, Soha Hassoun
**Guest Editors' Introduction: On-Chip Power Distribution Networks.**[Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2003, v:20, n:3, pp:5-6 [Journal] - Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
**A multigrid-like technique for power grid analysis.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1148-1160 [Journal] - Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
**FABRICS II: A Statistically Based IC Fabrication Process Simulator.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:1, pp:40-46 [Journal] - Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
**A Methodology for Worst-Case Analysis of Integrated Circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:104-113 [Journal] - Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
**Early-stage power grid analysis for uncertain working modes.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:676-682 [Journal] - Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
**Power grid analysis using random walks.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1204-1224 [Journal] - Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
**A methodology for the simultaneous design of supply and signal networks.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1614-1624 [Journal] - Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
**Optimal decoupling capacitor sizing and placement for standard-cell layout designs.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:428-436 [Journal] - Ritu Singhal, Asha Balijepalli, Anupama Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao
**Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:823-828 [Conf] - Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
**Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:148-153 [Conf] - Kanak Agarwal, Sani R. Nassif
**Characterizing Process Variation in Nanometer CMOS.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:396-399 [Conf] - Emrah Acar, Kanak Agarwal, Sani R. Nassif
**Characterization of total chip leakage using inverse (reciprocal) gamma distribution.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Sani R. Nassif, Kanak Agarwal, Emrah Acar
**Methods for estimating decoupling capacitance of nonswitching circuit blocks.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
**Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction**[Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal] - Emrah Acar, Anirudh Devgan, Sani R. Nassif
**Leakage and Leakage Sensitivity Computation for Combinational Circuits.**[Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2005, v:1, n:2, pp:172-181 [Journal] **Technology modeling and characterization beyond the 45nm node.**[Citation Graph (, )][DBLP]**Power grid analysis benchmarks.**[Citation Graph (, )][DBLP]**Analytical model for the impact of multiple input switching noise on timing.**[Citation Graph (, )][DBLP]**Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.**[Citation Graph (, )][DBLP]**Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level.**[Citation Graph (, )][DBLP]**Analyzing the impact of process variations on parametric measurements: Novel models and applications.**[Citation Graph (, )][DBLP]**A resilience roadmap.**[Citation Graph (, )][DBLP]**A methodology for propagating design tolerances to shape tolerances for use in manufacturing.**[Citation Graph (, )][DBLP]**MAPS: multi-algorithm parallel circuit simulation.**[Citation Graph (, )][DBLP]**Yield estimation of SRAM circuits using "Virtual SRAM Fab".**[Citation Graph (, )][DBLP]**Simultaneous layout migration and decomposition for double patterning technology.**[Citation Graph (, )][DBLP]**An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects.**[Citation Graph (, )][DBLP]**SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.**[Citation Graph (, )][DBLP]**Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives.**[Citation Graph (, )][DBLP]**Physical design challenges beyond the 22nm node.**[Citation Graph (, )][DBLP]**Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.**[Citation Graph (, )][DBLP]**A Root-Finding Method for Assessing SRAM Stability.**[Citation Graph (, )][DBLP]**A Design Model for Random Process Variability.**[Citation Graph (, )][DBLP]**Statistical yield analysis of silicon-on-insulator embedded DRAM.**[Citation Graph (, )][DBLP]**The impact of BEOL lithography effects on the SRAM cell performance and yield.**[Citation Graph (, )][DBLP]**Model to Hardware Matching for nm Scale Technologies.**[Citation Graph (, )][DBLP]**Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.**[Citation Graph (, )][DBLP]**Guest Editors' Introduction: Process Variation and Stochastic Design and Test.**[Citation Graph (, )][DBLP]**'Tis the gift to be simple.**[Citation Graph (, )][DBLP]
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