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Publications of Author

1. Naoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka
   Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:29-30 [Conf]
   
2. Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka
   Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:551-552 [Conf]
   
3. Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida
   A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:434-443 [Conf]
   
4. Takashi Hashimoto, Kazuaki Murakami, Tetsuo Hironaka, Hiroto Yasuura
   A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. [Citation Graph (0, 0)][DBLP]
   International Conference on Supercomputing, 1993, pp:308-317 [Conf]
   
5. Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki Murakami, Shinji Tomita
   Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. [Citation Graph (0, 0)][DBLP]
   ICS, 1992, pp:272-281 [Conf]
   
6. Takahiro Sasaki, Tetsuo Hironaka, Seiji Fujino
   Performance Improvements of Thakore's Algorithm with Speculative Execution Technique and Dynamic Task Scheduling. [Citation Graph (0, 0)][DBLP]
   Informatica (Slovenia), 2000, v:24, n:1, pp:- [Journal]
   
7. Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide
   Chip size and performance evaluations of shared cache for on-chip multiprocessor. [Citation Graph (0, 0)][DBLP]
   Systems and Computers in Japan, 2005, v:36, n:9, pp:1-13 [Journal]
   
8. Takahiro Sasaki, Tetsuo Hironaka, Naoki Nishimura, Noriyoshi Yoshida
   Scheduling support hardware for multiprocessor system and its evaluations. [Citation Graph (0, 0)][DBLP]
   Systems and Computers in Japan, 2006, v:37, n:2, pp:79-95 [Journal]
   
9. 
   Exploring compact design on high throughput coarse grained reconfigurable architectures. [Citation Graph (, )][DBLP]
   
   
10. 
    Design of superscalar processor with multi-bank register file. [Citation Graph (, )][DBLP]
    
    
11. 
    Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. [Citation Graph (, )][DBLP]
    
    
12. 
    Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. [Citation Graph (, )][DBLP]