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Katarzyna Radecka: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Katarzyna Radecka, Zeljko Zilic
    Identifying Redundant Wire Replacements for Synthesis and Verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:517-523 [Conf]
  2. Katarzyna Radecka, Zeljko Zilic
    Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:128-131 [Conf]
  3. Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka
    FPGA Emulation of Quantum Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:310-315 [Conf]
  4. Katarzyna Radecka, Zeljko Zilic
    Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:348-353 [Conf]
  5. Zeljko Zilic, Katarzyna Radecka
    The Role of Super-Fast Transforms in Speeding Up Quantum Computations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:129-135 [Conf]
  6. Zeljko Zilic, Katarzyna Radecka
    On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. [Citation Graph (0, 0)][DBLP]
    ISSAC, 1999, pp:67-74 [Conf]
  7. Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka
    Architectures of Increased Availability Wireless Sensor Network Nodes. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1232-1241 [Conf]
  8. Zeljko Zilic, Katarzyna Radecka
    : Identifying redundant gate replacements in verification by error modeling. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:803-812 [Conf]
  9. Katarzyna Radecka, Zeljko Zilic
    Identifying Redundant Wire Replacements for Synthesis and Verification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:517-523 [Conf]
  10. Katarzyna Radecka, Zeljko Zilic
    Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:271-280 [Conf]
  11. Rong Zhang, Zeljko Zilic, Katarzyna Radecka
    Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:186-191 [Conf]
  12. Katarzyna Radecka, Zeljko Zilic
    Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:5, pp:628-640 [Journal]
  13. Zeljko Zilic, Katarzyna Radecka
    Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:2, pp:202-207 [Journal]
  14. Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer
    Arithmetic built-in self-test for DSP cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1358-1369 [Journal]
  15. Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur
    Reversible circuit technology mapping from non-reversible specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:558-563 [Conf]

  16. Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. [Citation Graph (, )][DBLP]

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