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Zeljko Zilic: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Katarzyna Radecka, Zeljko Zilic
    Identifying Redundant Wire Replacements for Synthesis and Verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:517-523 [Conf]
  2. Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic
    Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:427-432 [Conf]
  3. Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic
    Design methodology for wireless nodes with printed antennas. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:291-296 [Conf]
  4. A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
    Design and Implementation of the NUMAchine Multiprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:66-69 [Conf]
  5. Ian Brynjolfson, Zeljko Zilic
    FPGA clock management for low power applications (poster abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:219- [Conf]
  6. Yongquan Fan, Zeljko Zilic
    Testing for bit error rate in FPGA communication interfaces. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:243- [Conf]
  7. Stuart McCracken, Zeljko Zilic
    FPGA test time reduction through a novel interconnect testing scheme. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:136-144 [Conf]
  8. Zeljko Zilic, Zvonko G. Vranesic
    Using BDDs to Design ULMs for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:24-30 [Conf]
  9. Atanu Chattopadhyay, Zeljko Zilic
    A globally asynchronous locally dynamic system for ASICs and SoCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:176-181 [Conf]
  10. Katarzyna Radecka, Zeljko Zilic
    Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:128-131 [Conf]
  11. Marc Boule, Zeljko Zilic
    Incorporating Ef.cient Assertion Checkers into Hardware Emulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:221-228 [Conf]
  12. Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka
    FPGA Emulation of Quantum Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:310-315 [Conf]
  13. Katarzyna Radecka, Zeljko Zilic
    Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:348-353 [Conf]
  14. R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
    The NUMAchine Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:487-496 [Conf]
  15. Ian Brynjolfson, Zeljko Zilic
    A new PLL design for clock management applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:814-817 [Conf]
  16. Yongquan Fan, Zeljko Zilic
    A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:877-880 [Conf]
  17. Boris Polianskikh, Zeljko Zilic
    Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:89-95 [Conf]
  18. Zeljko Zilic, Katarzyna Radecka
    The Role of Super-Fast Transforms in Speeding Up Quantum Computations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:129-135 [Conf]
  19. Zeljko Zilic, Zvonko G. Vranesic
    Current-Mode CMOS Galois Field Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:245-250 [Conf]
  20. Zeljko Zilic, Zvonko G. Vranesic
    Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:36-43 [Conf]
  21. Zeljko Zilic, Zvonko G. Vranesic
    New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:16-23 [Conf]
  22. Henry H. Y. Chan, Zeljko Zilic
    Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:309-314 [Conf]
  23. Henry H. Y. Chan, Zeljko Zilic
    Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:390-395 [Conf]
  24. Yongquan Fan, Zeljko Zilic, Man Wah Chiang
    A Versatile High Speed Bit Error Rate Testing Scheme. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:395-400 [Conf]
  25. Stuart McCracken, Zeljko Zilic
    Design for Testability of FPGA Blocks. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:86-91 [Conf]
  26. Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
    Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:613-620 [Conf]
  27. Zeljko Zilic, Katarzyna Radecka
    On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. [Citation Graph (0, 0)][DBLP]
    ISSAC, 1999, pp:67-74 [Conf]
  28. Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka
    Architectures of Increased Availability Wireless Sensor Network Nodes. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1232-1241 [Conf]
  29. Zeljko Zilic, Katarzyna Radecka
    : Identifying redundant gate replacements in verification by error modeling. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:803-812 [Conf]
  30. Jean-Samuel Chenard, Ahmed Usman Khalid, M. Prokic, Rong Zhang, K.-L. Lim, Atanu Chattopadhyay, Zeljko Zilic
    Expandable and Robust Laboratory for Microprocessor Systems. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:65-66 [Conf]
  31. Zeljko Zilic
    Alternatives in Teaching System-Building Skills. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:57-58 [Conf]
  32. Katarzyna Radecka, Zeljko Zilic
    Identifying Redundant Wire Replacements for Synthesis and Verification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:517-523 [Conf]
  33. Man Wah Chiang, Zeljko Zilic
    Layered Approach to Designing System Test Interfaces. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:331-338 [Conf]
  34. Katarzyna Radecka, Zeljko Zilic
    Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:271-280 [Conf]
  35. Rong Zhang, Zeljko Zilic, Katarzyna Radecka
    Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:186-191 [Conf]
  36. Katarzyna Radecka, Zeljko Zilic
    Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:5, pp:628-640 [Journal]
  37. Zeljko Zilic, Katarzyna Radecka
    Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:2, pp:202-207 [Journal]
  38. Zeljko Zilic, Zvonko G. Vranesic
    A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:9, pp:1100-1105 [Journal]
  39. Zeljko Zilic, Zvonko G. Vranesic
    A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:8, pp:1012-1020 [Journal]
  40. Zeljko Zilic, Zvonko G. Vranesic
    Using Decision Diagrams to Design ULMs for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:9, pp:970-982 [Journal]
  41. Knockaert Radecka, Zeljko Zilic
    Arithmetic transforms for compositions of sequential and imprecise datapaths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1382-1391 [Journal]
  42. Atanu Chattopadhyay, Zeljko Zilic
    GALDS: a complete framework for designing multiclock ASICs and SoCs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:641-654 [Journal]
  43. Henry H. Y. Chan, Zeljko Zilic
    Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:430-435 [Conf]
  44. Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur
    Reversible circuit technology mapping from non-reversible specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:558-563 [Conf]
  45. Atanu Chattopadhyay, Zeljko Zilic
    Reconfigurable Clock Distribution Circuitry. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:877-880 [Conf]
  46. Henry H. Y. Chan, Zeljko Zilic
    A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2934-2937 [Conf]
  47. Stephan Bourduas, Zeljko Zilic
    A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:195-204 [Conf]

  48. Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing. [Citation Graph (, )][DBLP]


  49. Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. [Citation Graph (, )][DBLP]


  50. Serial reconfigurable mismatch-tolerant clock distribution. [Citation Graph (, )][DBLP]


  51. Built-in Clock Skew System for On-line Debug and Repair. [Citation Graph (, )][DBLP]


  52. Enabling efficient post-silicon debug by clustering of hardware-assertions. [Citation Graph (, )][DBLP]


  53. Reliability aware NoC router architecture using input channel buffer sharing. [Citation Graph (, )][DBLP]


  54. MYGEN: automata-based on-line test generator for assertion-based verification. [Citation Graph (, )][DBLP]


  55. Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. [Citation Graph (, )][DBLP]


  56. Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age. [Citation Graph (, )][DBLP]


  57. Accelerating jitter tolerance qualification for high speed serial interfaces. [Citation Graph (, )][DBLP]


  58. A Quality-Driven Design Approach for NoCs. [Citation Graph (, )][DBLP]


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