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Diana Marculescu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Koushik Niyogi, Diana Marculescu
    Speed and voltage selection for GALS systems based on voltage/frequency islands. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:292-297 [Conf]
  2. Venkata Syam P. Rapaka, Emil Talpes, Diana Marculescu
    Mixed-clock issue queue design for energy aware, high-performance cores. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:380-383 [Conf]
  3. Puru Choudhary, Diana Marculescu
    Hardware based frequency/voltage control of voltage frequency island systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:34-39 [Conf]
  4. Diana Marculescu, Radu Marculescu, Pradeep K. Khosla
    Challenges and opportunities in electronic textiles modeling and optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:175-180 [Conf]
  5. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Efficient Power Estimation for Highly Correlated Input Streams. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:628-634 [Conf]
  6. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:696-701 [Conf]
  7. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Sequence Compaction for Probabilistic Analysis of Finite-State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:12-15 [Conf]
  8. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Hierarchical Sequence Compaction for Power Estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:570-575 [Conf]
  9. Diana Marculescu, Emil Talpes
    Variability and energy awareness: a microarchitecture-level perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:11-16 [Conf]
  10. Natasa Miskov-Zivanov, Diana Marculescu
    MARS-C: modeling and reduction of soft errors in combinational circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:767-772 [Conf]
  11. Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, Massoud Pedram
    Improving the Efficiency of Power Simulators by Input Vector Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:165-168 [Conf]
  12. Steve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu
    Dynamic Functional Unit Assignment for Low Power. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11052-11057 [Conf]
  13. Anoop Iyer, Diana Marculescu
    Power aware microarchitecture resource scaling. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:190-196 [Conf]
  14. Menno Lindwer, Diana Marculescu, Twan Basten, Rainer Zimmermann, Radu Marculescu, Stefan Jung, Eugenio Cantatore
    Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10010-10017 [Conf]
  15. Diana Marculescu
    Energy Bounds for Fault-Tolerant Nanoscale Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:74-79 [Conf]
  16. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:774-0 [Conf]
  17. Venkata Syam P. Rapaka, Diana Marculescu
    Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10504-10509 [Conf]
  18. Phillip Stanley-Marbell, Diana Marculescu
    Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:968-973 [Conf]
  19. Anoop Iyer, Diana Marculescu
    Power efficiency of voltage scaling in multiple clock, multiple voltage cores. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:379-386 [Conf]
  20. Diana Marculescu, Anoop Iyer
    Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:306-313 [Conf]
  21. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Switching activity analysis considering spatiotemporal correlations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:294-299 [Conf]
  22. Diana Marculescu, Nicholas H. Zamora, Phillip Stanley-Marbell, Radu Marculescu
    Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:348-355 [Conf]
  23. Phillip Stanley-Marbell, Diana Marculescu
    Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:633-640 [Conf]
  24. Diana Marculescu, Siddharth Garg
    System-level process-driven variability analysis for single and multiple voltage-frequency island systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:541-546 [Conf]
  25. Radu Marculescu, Diana Marculescu, Larry T. Pileggi
    Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:168-173 [Conf]
  26. Anoop Iyer, Diana Marculescu
    Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:158-0 [Conf]
  27. Emil Talpes, Diana Marculescu
    Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:310-321 [Conf]
  28. Diana Marculescu
    Profile-driven code execution for low power dissipation (poster session). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:253-255 [Conf]
  29. Diana Marculescu
    Application adaptive energy efficient clustered architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:344-349 [Conf]
  30. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Information theoretic measures of energy consumption at register transfer level. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:81-86 [Conf]
  31. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Composite sequence compaction for finite-state machines using block entropy and high-order Markov models. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:190-195 [Conf]
  32. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Theoretical bounds for switching activity analysis in finite-state machines. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:36-41 [Conf]
  33. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Non-stationary effects in trace-driven power analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:133-138 [Conf]
  34. Koushik Niyogi, Diana Marculescu
    System level power and performance modeling of GALS point-to-point communication interfaces. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:381-386 [Conf]
  35. Venkata Syam P. Rapaka, Diana Marculescu
    A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:372-377 [Conf]
  36. Emil Talpes, Diana Marculescu
    Power reduction through work reuse. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:340-345 [Conf]
  37. Emil Talpes, Diana Marculescu
    A critical analysis of application-adaptive multiple clock processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:278-281 [Conf]
  38. Emil Talpes, Diana Marculescu
    Impact of technology scaling on energy aware execution cache-based microarchitectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:50-53 [Conf]
  39. Radu Marculescu, Diana Marculescu
    Does Q=MC2? (On the Relationship between Quality in Electronic Design and the Model of Colloidal Computing, invited). [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:451-457 [Conf]
  40. Natasa Miskov-Zivanov, Diana Marculescu
    MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:893-898 [Conf]
  41. Chan-Hao Chang, Diana Marculescu
    Design and Analysis of a Low Power VLIW DSP Core. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:167-172 [Conf]
  42. Pradip Bose, David H. Albonesi, Diana Marculescu
    Guest Editors' Introduction: Power and Complexity Aware Design. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:8-11 [Journal]
  43. Diana Marculescu, Emil Talpes
    Energy Awareness and Uncertainty in Microarchitecture-Level Design. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:5, pp:64-76 [Journal]
  44. Phillip Stanley-Marbell, Diana Marculescu, Radu Marculescu, Pradeep K. Khosla
    Modeling, Analysis, and Self-Management of Electronic Textiles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:8, pp:996-1010 [Journal]
  45. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Information theoretic measures for power analysis [logic design]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:599-610 [Journal]
  46. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Probabilistic modeling of dependencies during switching activity analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:73-83 [Journal]
  47. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Sequence compaction for power estimation: theory and practice. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:973-993 [Journal]
  48. Philip Koopman, Howie Choset, Rajeev Gandhi, Bruce H. Krogh, Diana Marculescu, Priya Narasimhan, JoAnn M. Paul, Ragunathan Rajkumar, Daniel P. Siewiorek, Asim Smailagic, Peter Steenkiste, Donald E. Thomas, Chenxi Wang
    Undergraduate embedded system education at Carnegie Mellon. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:3, pp:500-528 [Journal]
  49. Steve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu
    Dynamic Functional Unit Assignment for Low Power. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2005, v:31, n:1, pp:47-62 [Journal]
  50. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Stochastic sequential machine synthesis with application to constrained sequence generation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:658-681 [Journal]
  51. Emil Talpes, Diana Marculescu
    Execution cache-based microarchitecture for power-efficient superscalar processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:14-26 [Journal]
  52. Emil Talpes, Diana Marculescu
    Toward a multiple clock/voltage island design style for power-aware processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:591-603 [Journal]
  53. Ümit Y. Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu
    Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:110-115 [Conf]
  54. Siddharth Garg, Diana Marculescu
    Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:403-408 [Conf]
  55. Phillip Stanley-Marbell, Diana Marculescu
    An 0.9 × 1.2", low power, energy-harvesting system with custom multi-channel communication interface. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:15-20 [Conf]
  56. Natasa Miskov-Zivanov, Diana Marculescu
    Soft error rate analysis for sequential circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1436-1441 [Conf]
  57. Phillip Stanley-Marbell, Diana Marculescu
    Sunflower : Full-System, Embedded Microarchitecture Evaluation. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:168-182 [Conf]
  58. Diana Marculescu
    Energy Bounds for Fault-Tolerant Nanoscale Designs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  59. Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Puru Choudhary, Diana Marculescu, Michael Kaufman, Peter Nelson
    Challenges and Promising Results in NoC Prototyping Using FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:86-95 [Journal]
  60. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Theoretical bounds for switching activity analysis in finite-state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:335-339 [Journal]
  61. Anoop Iyer, Diana Marculescu
    Microarchitecture-level power management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:230-239 [Journal]

  62. Soft error rate reduction using redundancy addition and removal. [Citation Graph (, )][DBLP]


  63. On the impact of manufacturing process variations on the lifetime of sensor networks. [Citation Graph (, )][DBLP]


  64. System-level mitigation of WID leakage power variability using body-bias islands. [Citation Graph (, )][DBLP]


  65. Characterizing chip-multiprocessor variability-tolerance. [Citation Graph (, )][DBLP]


  66. Variation-adaptive feedback control for networks-on-chip with multiple clock domains. [Citation Graph (, )][DBLP]


  67. Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective. [Citation Graph (, )][DBLP]


  68. Formal modeling and reasoning for reliability analysis. [Citation Graph (, )][DBLP]


  69. Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level. [Citation Graph (, )][DBLP]


  70. Joint logic restructuring and pin reordering against NBTI-induced performance degradation. [Citation Graph (, )][DBLP]


  71. System-level process variability analysis and mitigation for 3D MPSoCs. [Citation Graph (, )][DBLP]


  72. Clock skew scheduling for soft-error-tolerant sequential circuits. [Citation Graph (, )][DBLP]


  73. Variation-aware dynamic voltage/frequency scaling. [Citation Graph (, )][DBLP]


  74. Process variability-aware transient fault modeling and analysis. [Citation Graph (, )][DBLP]


  75. Power-aware soft error hardening via selective voltage scaling. [Citation Graph (, )][DBLP]


  76. Analysis of dynamic voltage/frequency scaling in chip-multiprocessors. [Citation Graph (, )][DBLP]


  77. Custom feedback control: enabling truly scalable on-chip power management for MPSoCs. [Citation Graph (, )][DBLP]


  78. Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection. [Citation Graph (, )][DBLP]


  79. Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. [Citation Graph (, )][DBLP]


  80. A systematic approach to modeling and analysis of transient faults in logic circuits. [Citation Graph (, )][DBLP]


  81. 3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs. [Citation Graph (, )][DBLP]


  82. Architectures for Silicon Nanoelectronics and Beyond. [Citation Graph (, )][DBLP]


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