Koichi Nose, Soo-Ik Chae, Takayasu Sakurai Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). [Citation Graph (0, 0)][DBLP] ISLPED, 2000, pp:228-230 [Conf]
Koichi Nose, Takayasu Sakurai Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. [Citation Graph (0, 0)][DBLP] ISLPED, 2002, pp:24-29 [Conf]