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Anand Ramalingam: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan
    Robust analytical gate delay modeling for low voltage circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:61-66 [Conf]
  2. Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan
    Sleep transistor sizing using timing criticality and temporal currents. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1094-1097 [Conf]
  3. Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
    An accurate sparse matrix based framework for statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:231-236 [Conf]
  4. Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif
    Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:644-649 [Conf]
  5. Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
    Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:148-153 [Conf]
  6. Anand Ramalingam, Giri Devarayanadurg, David Z. Pan
    Accurate power grid analysis with behavioral transistor network modeling. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:43-50 [Conf]
  7. Anand Ramalingam, Anirudh Devgan, David Z. Pan
    Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:28-35 [Journal]

  8. Latch Modeling for Statistical Timing Analysis. [Citation Graph (, )][DBLP]


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