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Anand Ramalingam:
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 Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan
Robust analytical gate delay modeling for low voltage circuits. [Citation Graph (0, 0)][DBLP] ASPDAC, 2006, pp:6166 [Conf]
 Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan
Sleep transistor sizing using timing criticality and temporal currents. [Citation Graph (0, 0)][DBLP] ASPDAC, 2005, pp:10941097 [Conf]
 Anand Ramalingam, GiJoon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
An accurate sparse matrix based framework for statistical static timing analysis. [Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:231236 [Conf]
 Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif
Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. [Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:644649 [Conf]
 Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. [Citation Graph (0, 0)][DBLP] DAC, 2007, pp:148153 [Conf]
 Anand Ramalingam, Giri Devarayanadurg, David Z. Pan
Accurate power grid analysis with behavioral transistor network modeling. [Citation Graph (0, 0)][DBLP] ISPD, 2007, pp:4350 [Conf]
 Anand Ramalingam, Anirudh Devgan, David Z. Pan
Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. [Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2007, v:3, n:1, pp:2835 [Journal]
Latch Modeling for Statistical Timing Analysis. [Citation Graph (, )][DBLP]
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