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Publications of Author

1. Olivier Thomas, Marina Reyboz, Marc Belleville
   Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:2778-2781 [Conf]
   
2. 
   Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. [Citation Graph (, )][DBLP]
   
   
3. 
   Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. [Citation Graph (, )][DBLP]
   
   
4. 
   An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. [Citation Graph (, )][DBLP]