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Dajiang Zhou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dajiang Zhou, Peilin Liu
    A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2910-2913 [Conf]

  2. A 136 cycles/MB, luma-chroma parallelized H.264/AVC deblocking filter for QFHD applications. [Citation Graph (, )][DBLP]


  3. An advanced hierarchical motion estimation scheme with lossless frame recompression for ultra high definition video coding. [Citation Graph (, )][DBLP]


  4. An SDRAM controller optimized for high definition video coding application. [Citation Graph (, )][DBLP]


  5. A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding. [Citation Graph (, )][DBLP]


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