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Wenjing Rao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault tolerant nanoelectronic processor architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:311-316 [Conf]
  2. Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu
    Test application time and volume compression through seed overlapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:732-737 [Conf]
  3. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Topology aware mapping of logic functions onto nanowire-based crossbar architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:723-726 [Conf]
  4. Wenjing Rao, Alex Orailoglu
    Virtual Compression through Test Vector Stitching for Scan Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10104-10109 [Conf]
  5. Wenjing Rao, Alex Orailoglu, G. Su
    Frugal linear network-based test decompression for drastic test cost reductions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:721-725 [Conf]
  6. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:533-542 [Conf]
  7. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:472-478 [Conf]
  8. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:214-221 [Conf]
  9. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:865-869 [Conf]
  10. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:216-224 [Conf]
  11. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:63-68 [Conf]
  12. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Towards Nanoelectronics Processor Architectures. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:235-254 [Journal]

  13. Towards fault tolerant parallel prefix adders in nanoelectronic systems. [Citation Graph (, )][DBLP]


  14. Selective Hardening of NanoPLA Circuits. [Citation Graph (, )][DBLP]


  15. Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis. [Citation Graph (, )][DBLP]


  16. Logic Mapping in Crossbar-Based Nanoarchitectures. [Citation Graph (, )][DBLP]


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