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S. H. Rasouli:
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Publications of Author
- S. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali-Kusha
Double edge triggered Feedback Flip-Flop in sub 100NM technology. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:297-302 [Conf]
- Ali Abbasian, S. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani
No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:289-292 [Conf]
- A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology. [Citation Graph (0, 0)][DBLP] ISVLSI, 2006, pp:373-377 [Conf]
- A. Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, Ali Afzali-Kusha
Low power and high performance clock delayed domino logic using saturated keeper. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
Low power low leakage clock gated static pulsed flip-flop. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
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