The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

S. H. Rasouli: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. S. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali-Kusha
    Double edge triggered Feedback Flip-Flop in sub 100NM technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:297-302 [Conf]
  2. Ali Abbasian, S. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani
    No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:289-292 [Conf]
  3. A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
    Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:373-377 [Conf]
  4. A. Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, Ali Afzali-Kusha
    Low power and high performance clock delayed domino logic using saturated keeper. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  5. A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
    Low power low leakage clock gated static pulsed flip-flop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

Search in 0.002secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002