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A. Amirabadi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. S. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali-Kusha
    Double edge triggered Feedback Flip-Flop in sub 100NM technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:297-302 [Conf]
  2. A. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz
    Leakage current reduction by new technique in standby mode. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:158-161 [Conf]
  3. A. Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani
    Domino logic with an efficient variable threshold voltage keeper. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1674-1677 [Conf]
  4. A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
    Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:373-377 [Conf]
  5. A. Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, Ali Afzali-Kusha
    Low power and high performance clock delayed domino logic using saturated keeper. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  6. A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
    Low power low leakage clock gated static pulsed flip-flop. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  7. A. Amirabadi, Ali Afzali-Kusha, Y. Mortazavi, Mehrdad Nourani
    Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:125-134 [Journal]

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