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Juho Kim :
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Hidetoshi Onodera , Andrew B. Kahng , Wayne Wei-Ming Dai , Sani R. Nassif , Juho Kim , Akira Tanabe , Toshihiro Hattori Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2001, pp:267-268 [Conf ] Juho Kim , Cyrus Bamji , Yanbin Jiang , Sachin S. Sapatnekar Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. [Citation Graph (0, 0)][DBLP ] ISPD, 1997, pp:130-135 [Conf ] Juho Kim , David Hung-Chang Du Performance optimization by gate sizing and path sensitization. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:459-462 [Journal ] Yanbin Jiang , Sachin S. Sapatnekar , Cyrus Bamji , Juho Kim Interleaving buffer insertion and transistor sizing into a single optimization. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:625-633 [Journal ] Automatic retargeting of web page content. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.002secs