Search the dblp DataBase

Publications of Author

1. Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans
   MAIA: a framework for networks on chip generation and verification. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:49-52 [Conf]
   
2. Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes
   MultiNoC: A Multiprocessing System Enabled by a Network on Chip. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:234-239 [Conf]
   
3. Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes
   MultiNoC: A Multiprocessing System Enabled by a Network on Chip. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:234-239 [Conf]
   
4. Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes
   Virtual channels in networks on chip: implementation and evaluation on hermes NoC. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2005, pp:178-183 [Conf]
   
5. Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes
   Application driven traffic modeling for NoCs. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2006, pp:62-67 [Conf]
   
6. Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes
   Traffic generation and performance evaluation for mesh-based NoCs. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2005, pp:184-189 [Conf]
   
7. Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans
   A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2003, pp:318-323 [Conf]
   
8. Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost
   HERMES: an infrastructure for low area overhead packet-switching networks on chip. [Citation Graph (0, 0)][DBLP]
   Integration, 2004, v:38, n:1, pp:69-93 [Journal]
   
9. Everton Carara, Aline Mello, Fernando Moraes
   Communication Models in Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2007, pp:57-60 [Conf]
   
10. Aline Mello, Leandro Möller, Ney Calazans, Fernando Moraes
    MultiNoC: A Multiprocessing System Enabled by a Network on Chip [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
11. 
    Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations. [Citation Graph (, )][DBLP]
    
    
12. 
    Rate-based scheduling policy for QoS flows in networks on chip. [Citation Graph (, )][DBLP]