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Fernando Gehm Moraes: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans
    MAIA: a framework for networks on chip generation and verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:49-52 [Conf]
  2. Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
    Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:62-63 [Conf]
  3. César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel
    Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:502-507 [Conf]
  4. Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes
    MultiNoC: A Multiprocessing System Enabled by a Network on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:234-239 [Conf]
  5. Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes
    MultiNoC: A Multiprocessing System Enabled by a Network on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:234-239 [Conf]
  6. Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans
    Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11122-11123 [Conf]
  7. Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes
    Design of a fingerprint system using a hardware/software environment. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:240- [Conf]
  8. Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes
    Propose of a Hardware Implementation for Fingerprint Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1158-1161 [Conf]
  9. Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato
    FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1042-1046 [Conf]
  10. Daniel Mesquita, Fernando Gehm Moraes, José Palma, Leandro Möller, Ney Laert Vilar Calazans
    Remote and Partial Reconfiguration of FPGAs: Tools and Trends. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:177- [Conf]
  11. José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes
    Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:426-427 [Conf]
  12. José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Inserting Data Encoding Techniques into NoC-Based Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:299-304 [Conf]
  13. Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes
    Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:459-460 [Conf]
  14. José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
    Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:603-613 [Conf]
  15. José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin
    Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:196-201 [Conf]
  16. Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes
    Reducing test time with processor reuse in network-on-chip based systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:111-116 [Conf]
  17. Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes
    Application driven traffic modeling for NoCs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:62-67 [Conf]
  18. Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans
    A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:318-323 [Conf]
  19. Alexandre M. Amory, Leandro A. Oliveira, Fernando Gehm Moraes
    Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:174-179 [Conf]
  20. Daniel Mesquita, Lionel Torres, Fernando Gehm Moraes, Gilles Sassatelli, Michel Robert
    Are coarse grain reconfigurable architectures suitable for cryptography? [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:276-281 [Conf]
  21. Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost
    HERMES: an infrastructure for low area overhead packet-switching networks on chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:1, pp:69-93 [Journal]
  22. Ney Laert Vilar Calazans, Fernando Gehm Moraes, Delfim Luiz Torok, Andrey V. Andreoli
    Projeto para Prototipação de um IP Soft Core MAC Ethernet. [Citation Graph (0, 0)][DBLP]
    RITA, 2001, v:8, n:1, pp:23-41 [Journal]
  23. Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Jean-Claude Bajard, Fernando Gehm Moraes
    A Leak Resistant Architecture Against Side Channel Attacks. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  24. César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes
    Evaluation of Algorithms for Low Energy Mapping onto NoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:389-392 [Conf]
  25. Gilles Sassatelli, Nicolas Saint-Jean, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes
    Architectural Issues in Homogeneous NoC-Based MPSoC. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:139-142 [Conf]
  26. Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathebras, Gilles Sassatelli, Fernando Gehm Moraes
    Current Mask Generation: an Analog Circuit to Thwart DPA Attacks. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:317-330 [Conf]
  27. César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis
    Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:179-194 [Conf]
  28. César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel
    Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  29. Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
    Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  30. Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs. [Citation Graph (, )][DBLP]


  31. Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip. [Citation Graph (, )][DBLP]


  32. NoC Power Estimation at the RTL Abstraction Level. [Citation Graph (, )][DBLP]


  33. A simplified executable model to evaluate latency and throughput of networks-on-chip. [Citation Graph (, )][DBLP]


  34. MOTIM: an industrial application using nocs. [Citation Graph (, )][DBLP]


  35. A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. [Citation Graph (, )][DBLP]


  36. Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. [Citation Graph (, )][DBLP]


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