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Tay-Jyi Lin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
    A 52mW 1200MIPS compact DSP for multi-core media SoC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:118-119 [Conf]
  2. Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen
    A unified processor architecture for RISC & VLIW DSP. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:50-55 [Conf]
  3. Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
    A compact DSP core with static floating-point unit & its microcode generation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:57-60 [Conf]
  4. Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen
    An Efficient VLIW DSP Architecture for Baseband Processing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:307-312 [Conf]
  5. Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen
    Pipelining technique for energy-aware datapaths. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1218-1221 [Conf]
  6. Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
    Area-effective FIR filter design for multiplier-less implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:173-176 [Conf]
  7. Tay-Jyi Lin, Chein-Wei Jen
    An efficient 2-D DWT architecture via resource cycling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:914-917 [Conf]
  8. Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen
    Static floating-point unit with implicit exponent tracking for embedded DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:821-824 [Conf]
  9. Tay-Jyi Lin, Chein-Wei Jen
    CASCADE - configurable and scalable DSP environment. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:870-873 [Conf]
  10. Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
    Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3506-3509 [Conf]
  11. Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu
    Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:409-412 [Conf]
  12. Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen
    Programmable FIR filter with adder-based computing engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  13. Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen
    A Compact DSP Core with Static Floating-Point Arithmetic. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:2, pp:127-138 [Journal]

  14. Ultra low-power ANSI S1.11 filter bank for digital hearing aids. [Citation Graph (, )][DBLP]


  15. Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. [Citation Graph (, )][DBLP]


  16. Multithreaded coprocessor interface for multi-core multimedia SoC. [Citation Graph (, )][DBLP]


  17. RunAssert: A non-intrusive run-time assertion for parallel programs debugging. [Citation Graph (, )][DBLP]


  18. Collaborative voltage scaling with online STA and variable-latency datapath. [Citation Graph (, )][DBLP]


  19. Cycle Stealing and Channel Management for On-Chip Networks. [Citation Graph (, )][DBLP]


  20. Architecture for area-efficient 2-D transform in H.264/AVC. [Citation Graph (, )][DBLP]


  21. Hierarchical instruction encoding for VLIW digital signal processors. [Citation Graph (, )][DBLP]


  22. Complexity-effective auditory compensation for digital hearing aids. [Citation Graph (, )][DBLP]


  23. Improving datapathutilization of programmable DSP with composite functional units. [Citation Graph (, )][DBLP]


  24. Parallel object detection on multicore platforms. [Citation Graph (, )][DBLP]


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