The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Tsuneo Nakata: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata
    Formal verification based on assume and guarantee approach - a case study (short paper). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:77-80 [Conf]
  2. Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan
    Functional Verification of System on Chips-Practices, Issues and Challenges. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:11-13 [Conf]
  3. Kwame Osei Boateng, Hideaki Konishi, Tsuneo Nakata
    A Method of Static Compaction of Test Stimuli. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:137-144 [Conf]
  4. Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata
    System-on-chip validation using UML and CWL. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:92-97 [Conf]
  5. Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata
    Integrating UML into SoC Design Process. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:836-837 [Conf]
  6. Hiroaki Iwashita, Tsuneo Nakata
    Forward model checking techniques oriented to buggy designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:400-404 [Conf]
  7. Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose
    Automatic test program generation for pipelined processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:580-583 [Conf]
  8. Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose
    CTL model checking based on forward state traversal. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:82-87 [Conf]
  9. Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu
    An Object-Oriented Design Process for System-on-Chip Using UML. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:249-254 [Conf]
  10. Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro Kuroki, Yoichi Endo, Takashi Hasegawa
    System-on-Chip Verification Process Using UML. [Citation Graph (0, 0)][DBLP]
    UML Satellite Activities, 2004, pp:138-149 [Conf]
  11. Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata
    Dataflow Analysis for Resource Contention and Register Leakage Properties. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:418-423 [Conf]
  12. Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan
    Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:11-13 [Conf]
  13. Tsuneo Nakata
    Multi-event algorithms and protocols for fast and robust distributed mesh provisioning and restoration. [Citation Graph (0, 0)][DBLP]
    Bell Labs Technical Journal, 2003, v:7, n:3, pp:23-39 [Journal]

Search in 0.039secs, Finished in 0.040secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002