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Ziyad Hanna: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
    Generation of shorter sequences for high resolution error diagnosis using sequential SAT. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:25-29 [Conf]
  2. John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss
    CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:131-143 [Conf]
  3. Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna
    A proof engine approach to solving combinational design automation problems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:725-730 [Conf]
  4. Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
    A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:436-441 [Conf]
  5. Jacob Katz, Ziyad Hanna, Nachum Dershowitz
    Space-Efficient Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:686-687 [Conf]
  6. Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
    Post-reboot Equivalence and Compositional Verification of Hardware. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:11-18 [Conf]
  7. Zurab Khasidashvili, Alexander Nadel, Amit Palti, Ziyad Hanna
    Simultaneous SAT-Based Model Checking of Safety Properties. [Citation Graph (0, 0)][DBLP]
    Haifa Verification Conference, 2005, pp:56-75 [Conf]
  8. Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
    Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:58-65 [Conf]
  9. Sasha Novakovsky, Shy Shyman, Ziyad Hanna
    High capacity and automatic functional extraction tool for industrial VLSI circuit designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:520-525 [Conf]
  10. Nachum Dershowitz, Ziyad Hanna, Jacob Katz
    Bounded Model Checking with QBF. [Citation Graph (0, 0)][DBLP]
    SAT, 2005, pp:408-414 [Conf]
  11. Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
    A Scalable Algorithm for Minimal Unsatisfiable Core Extraction. [Citation Graph (0, 0)][DBLP]
    SAT, 2006, pp:36-41 [Conf]
  12. Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
    A Clause-Based Heuristic for SAT Solvers. [Citation Graph (0, 0)][DBLP]
    SAT, 2005, pp:46-60 [Conf]
  13. Marco Bozzano, Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Ziyad Hanna, Zurab Khasidashvili, Amit Palti, Roberto Sebastiani
    Encoding RTL Constructs for MathSAT: a Preliminary Report. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:144, n:2, pp:3-14 [Journal]
  14. Yulik Feldman, Nachum Dershowitz, Ziyad Hanna
    Parallel Multithreaded Satisfiability Solver: Design and Implementation. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2005, v:128, n:3, pp:75-90 [Journal]
  15. Zurab Khasidashvili, Ziyad Hanna
    SAT-based methods for sequential hardware equivalence verification without synchronization. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2003, v:89, n:4, pp:- [Journal]
  16. Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna
    A Signal Correlation Guided Circuit-SAT Solver. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2004, v:10, n:12, pp:1629-1654 [Journal]
  17. Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna
    Design automation with mixtures of proof strategies for propositional logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1042-1048 [Journal]
  18. Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Alberto Griggio, Ziyad Hanna, Alexander Nadel, Amit Palti, Roberto Sebastiani
    A Lazy and Layered SMT($\mathcal{BV}$) Solver for Hard Industrial Verification Problems. [Citation Graph (0, 0)][DBLP]
    CAV, 2007, pp:547-560 [Conf]
  19. Ziyad Hanna
    Abstract Modeling and Formal Verification of Microprocessors. [Citation Graph (0, 0)][DBLP]
    CSR, 2007, pp:23- [Conf]
  20. Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
    Towards a Better Understanding of the Functionality of a Conflict-Driven SAT Solver. [Citation Graph (0, 0)][DBLP]
    SAT, 2007, pp:287-293 [Conf]
  21. Nachum Dershowitz, Ziyad Hanna, Alexander Nadel
    A Scalable Algorithm for Minimal Unsatisfiable Core Extraction [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  22. Jacob Katz, Ziyad Hanna, Nachum Dershowitz
    Space-Efficient Bounded Model Checking [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  23. Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification. [Citation Graph (, )][DBLP]


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