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Rafael Ruiz-Sautua: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Arrival time aware scheduling to minimize clock cycle length. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1018-1021 [Conf]
  2. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Behavioural Bitwise Scheduling Based on Computational Effort Balancing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:684-685 [Conf]
  3. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1252-1257 [Conf]
  4. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Pre-synthesis optimization of multiplications to improve circuit performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1306-1311 [Conf]
  5. Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida
    Performance-driven read-after-write dependencies softening in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:7-12 [Conf]
  6. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Behavioural Scheduling to Balance the Bit-Level Computational Effort. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:99-104 [Conf]
  7. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:617-627 [Conf]
  8. María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
    Bitwise scheduling to balance the computational cost of behavioral specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:31-46 [Journal]
  9. María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
    Area optimization of multi-cycle operators in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:449-454 [Conf]
  10. Rafael Ruiz-Sautua, María C. Molina, Joé M. Mendias, Román Hermida
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  11. Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits. [Citation Graph (, )][DBLP]


  12. Subword Switching Activity Minimization to Optimize Dynamic Power Consumption. [Citation Graph (, )][DBLP]


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