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María C. Molina: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Arrival time aware scheduling to minimize clock cycle length. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1018-1021 [Conf]
  2. María C. Molina, José M. Mendías, Román Hermida
    High-level synthesis of multiple-precision circuitsindependent of data-objects length. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:612-615 [Conf]
  3. María C. Molina, José M. Mendías, Román Hermida
    Multiple-Precision Circuits Allocation Independent of Data-Objects Length. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:909-915 [Conf]
  4. María C. Molina, José M. Mendías, Román Hermida
    High-Level Allocation to Minimize Internal Hardware Wastage. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10264-10269 [Conf]
  5. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Behavioural Bitwise Scheduling Based on Computational Effort Balancing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:684-685 [Conf]
  6. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1252-1257 [Conf]
  7. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Pre-synthesis optimization of multiplications to improve circuit performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1306-1311 [Conf]
  8. José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba
    Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:308-315 [Conf]
  9. María C. Molina, José M. Mendías, Román Hermida
    Bit-Level Allocation of Multiple-Precision Specifications. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:385-392 [Conf]
  10. María C. Molina, José M. Mendías, Román Hermida
    Bit-level scheduling of heterogeneous behavioural specifications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:602-608 [Conf]
  11. Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida
    Performance-driven read-after-write dependencies softening in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:7-12 [Conf]
  12. Olga Peñalba, José M. Mendías, María C. Molina
    Execution Condition Analysis in High Level Synthesis: A Unified Approach. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:73-78 [Conf]
  13. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Behavioural Scheduling to Balance the Bit-Level Computational Effort. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:99-104 [Conf]
  14. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:617-627 [Conf]
  15. María C. Molina, José M. Mendías, Román Hermida
    Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:505-519 [Journal]
  16. María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
    Bitwise scheduling to balance the computational cost of behavioral specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:31-46 [Journal]
  17. María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
    Area optimization of multi-cycle operators in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:449-454 [Conf]
  18. Rafael Ruiz-Sautua, María C. Molina, Joé M. Mendias, Román Hermida
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  19. Using Speculative Functional Units in high level synthesis. [Citation Graph (, )][DBLP]


  20. Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. [Citation Graph (, )][DBLP]


  21. Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits. [Citation Graph (, )][DBLP]


  22. Enhanced gradient-based motion vector coprocessor. [Citation Graph (, )][DBLP]


  23. Applying speculation techniques to implement functional units. [Citation Graph (, )][DBLP]


  24. Subword Switching Activity Minimization to Optimize Dynamic Power Consumption. [Citation Graph (, )][DBLP]


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