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José M. Mendías: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Arrival time aware scheduling to minimize clock cycle length. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1018-1021 [Conf]
  2. María C. Molina, José M. Mendías, Román Hermida
    High-level synthesis of multiple-precision circuitsindependent of data-objects length. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:612-615 [Conf]
  3. José M. Mendías, Román Hermida
    Correct High-Level Synthesis: a Formal Perspective. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:977-978 [Conf]
  4. María C. Molina, José M. Mendías, Román Hermida
    Multiple-Precision Circuits Allocation Independent of Data-Objects Length. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:909-915 [Conf]
  5. María C. Molina, José M. Mendías, Román Hermida
    High-Level Allocation to Minimize Internal Hardware Wastage. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10264-10269 [Conf]
  6. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Behavioural Bitwise Scheduling Based on Computational Effort Balancing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:684-685 [Conf]
  7. Olga Peñalba, José M. Mendías, Román Hermida
    Maximizing Conditonal Reuse by Pre-Synthesis Transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1097- [Conf]
  8. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1252-1257 [Conf]
  9. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Pre-synthesis optimization of multiplications to improve circuit performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1306-1311 [Conf]
  10. Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida
    Optimization of Equational Specifications Using Genetic Techniques. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:252-258 [Conf]
  11. Olga Peñalba, José M. Mendías, Román Hermida
    Source Code Transformation to Improve Conditional Hardware Reuse. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:324-331 [Conf]
  12. José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba
    Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:308-315 [Conf]
  13. María C. Molina, José M. Mendías, Román Hermida
    Bit-Level Allocation of Multiple-Precision Specifications. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:385-392 [Conf]
  14. Olga Peñalba, José M. Mendías, Román Hermida
    A Unified Algorithm for Mutual Exclusiveness Identification. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1504-1510 [Conf]
  15. María C. Molina, José M. Mendías, Román Hermida
    Bit-level scheduling of heterogeneous behavioural specifications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:602-608 [Conf]
  16. Olga Peñalba, José M. Mendías, María C. Molina
    Execution Condition Analysis in High Level Synthesis: A Unified Approach. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:73-78 [Conf]
  17. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Behavioural Scheduling to Balance the Bit-Level Computational Effort. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:99-104 [Conf]
  18. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:617-627 [Conf]
  19. José M. Mendías, Román Hermida, Milagros Fernández
    Formal Techniques for Hardware Allocation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:161-165 [Conf]
  20. Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis
    Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. [Citation Graph (0, 0)][DBLP]
    WWIC, 2005, pp:354-364 [Conf]
  21. José M. Mendías, Román Hermida, Olga Peñalba
    A study about the efficiency of formal high-level synthesis applied to verification. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:31, n:2, pp:101-131 [Journal]
  22. María C. Molina, José M. Mendías, Román Hermida
    Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:505-519 [Journal]
  23. Edgar G. Daylight, David Atienza, Arnout Vandecappelle, Francky Catthoor, José M. Mendías
    Memory-access-aware data structure transformations for embedded software with dynamic data accesses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:269-280 [Journal]
  24. Rafael Ruiz-Sautua, María C. Molina, Joé M. Mendias, Román Hermida
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

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