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Manoj Sachdev: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Stefan Rusu, Manoj Sachdev, Christer Svensson, B. Nauta
    T3: Trends and Challenges in VLSI Technology Scaling towards 100nm. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:16-17 [Conf]
  2. Arman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
    Design optimizations for microprocessors at low temperature. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:2-5 [Conf]
  3. Muhammad Nummer, Manoj Sachdev
    DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10212-10217 [Conf]
  4. Manoj Sachdev
    Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:319-326 [Conf]
  5. Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi
    Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:12-19 [Conf]
  6. Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi
    Thermal Management of High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:313-319 [Conf]
  7. Manoj Sachdev
    Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:361-365 [Conf]
  8. Christine Kwong, Bhaskar Chatterjee, Manoj Sachdev
    Modeling and designing energy-delay optimized wide domino circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:921-924 [Conf]
  9. Nitin Mohan, Manoj Sachdev
    Low power dual matchline ternary content addressable memory. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:633-636 [Conf]
  10. Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
    Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:122-127 [Conf]
  11. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
    A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:248-251 [Conf]
  12. Mohamed Elgebaly, Manoj Sachdev
    Efficient adaptive voltage scaling system through on-chip critical path emulation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:375-380 [Conf]
  13. Rafael Llopis, Manoj Sachdev
    Low power, testable dual edge triggered flip-flops. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:341-345 [Conf]
  14. James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
    Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:147-152 [Conf]
  15. Mohammad Sharifkhani, Manoj Sachdev
    A low power SRAM architecture based on segmented virtual grounding. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:256-261 [Conf]
  16. Shahab Ardalan, Manoj Sachdev
    An Overview of Substrate Noise Reduction Techniques. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:291-296 [Conf]
  17. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
    Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:415-420 [Conf]
  18. Oleg Semenov, H. Sarbishaei, Manoj Sachdev
    Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:427-432 [Conf]
  19. David Rennie, Manoj Sachdev
    Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:305-310 [Conf]
  20. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1130-1139 [Conf]
  21. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1108-1117 [Conf]
  22. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, K. Soumyanath, Vivek De
    Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1051-1059 [Conf]
  23. Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez
    AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1006-1015 [Conf]
  24. Manoj Sachdev
    Multi-GHz Interface Devices Should Be Tested Using External Test Resources. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1231- [Conf]
  25. Manoj Sachdev
    IDDQ and Voltage Testable CMOS Flip-flop Configurations. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:534-543 [Conf]
  26. Manoj Sachdev
    Deep Sub-micron IDDQ Test Options. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:942- [Conf]
  27. Manoj Sachdev, Bert Atzema
    Industrial Relevance of Analog IFA: A Fact or a Fiction. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:61-70 [Conf]
  28. Manoj Sachdev, Peter Janssen, Victor Zieren
    Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:204- [Conf]
  29. Manoj Sachdev, Math Verstraelen
    Development of Fault Model and Test Algorithms for Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:815-824 [Conf]
  30. Oleg Semenov, Arman Vassighi, Manoj Sachdev, Ali Keshavarzi, Charles F. Hawkins
    Burn-in Temperature Projections for Deep Sub-micron Technologies. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:95-104 [Conf]
  31. Mansour Shashaani, Manoj Sachdev
    A DFT technique for high performance circuit testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:276-285 [Conf]
  32. Derek Wright, Manoj Sachdev
    Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:39-47 [Conf]
  33. Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev
    Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:55-64 [Conf]
  34. Stefan Rusu, Manoj Sachdev, Christer Svensson, B. Nauta
    Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:16-17 [Conf]
  35. Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
    A Low-Speed BIST Framework for High-Performance Circuit Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:349-358 [Conf]
  36. Muhammad Nummer, Manoj Sachdev
    A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:68-74 [Conf]
  37. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    DFT for Delay Fault Testing of High-Performance Digital Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:248-258 [Journal]
  38. Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
    Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:36-43 [Journal]
  39. Manoj Sachdev
    Current-Based Testing for Deep-Submicron VLSIs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:2, pp:76-84 [Journal]
  40. Manoj Sachdev
    Testing Defects in Scan Chains. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:4, pp:45-51 [Journal]
  41. Manoj Sachdev
    Open Defects in CMOS RAM Address Decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:2, pp:26-33 [Journal]
  42. Manoj Sachdev, Hans G. Kerkhoff
    Configurations for IDDQ-Testable PLAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:2, pp:58-65 [Journal]
  43. Muhammad Nummer, Manoj Sachdev
    Testing high-performance pipelined circuits with slow-speed testers. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:506-521 [Journal]
  44. Farhad H. A. Asgari, Manoj Sachdev
    A low-power reduced swing global clocking methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:5, pp:538-545 [Journal]
  45. Bhaskar Chatterjee, Manoj Sachdev
    Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1296-1304 [Journal]
  46. M. Maymandi-Nejad, Manoj Sachdev
    Correction to "A Digitally Programmable Delay Element: Design and Analysis". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1126-1126 [Journal]
  47. Nitin Mohan, W. Fung, Derek Wright, Manoj Sachdev
    Design techniques and test methodology for low-power TCAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:573-586 [Journal]
  48. M. Maymandi-Nejad, Manoj Sachdev
    DTMOS Technique for Low-Voltage Analog Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1151-1156 [Journal]
  49. Oleg Semenov, H. Sarbishaei, Valery Axelrad, Manoj Sachdev
    Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:6, pp:526-533 [Journal]
  50. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
    Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:9, pp:801-809 [Journal]
  51. David Rennie, Manoj Sachdev
    A Novel Tri-State Binary Phase Detector. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:185-188 [Conf]
  52. Mohammad Sharifkhani, Manoj Sachdev
    A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  53. Mohammad Sharifkhani, Manoj Sachdev
    Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:196-205 [Journal]
  54. Mohamed Elgebaly, Manoj Sachdev
    Variation-Aware Adaptive Voltage Scaling System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:560-571 [Journal]
  55. M. Maymandi-Nejad, Manoj Sachdev
    A digitally programmable delay element: design and analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:871-878 [Journal]
  56. Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh
    New JETTA Editors, 2006. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:9-10 [Journal]

  57. A 0.8V Delta-Sigma modulator using DTMOS technique. [Citation Graph (, )][DBLP]


  58. A fully digital ADC using a new delay element with enhanced linearity. [Citation Graph (, )][DBLP]


  59. Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model. [Citation Graph (, )][DBLP]


  60. Comparative analysis and study of metastability on high-performance flip-flops. [Citation Graph (, )][DBLP]


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