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Preeti Ranjan Panda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Preeti Ranjan Panda
    Abridged addressing: a low power memory addressing strategy. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:892-897 [Conf]
  2. Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
    Rapid estimation of control delay from high-level specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:455-458 [Conf]
  3. Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
    An integrated algorithm for memory allocation and assignment in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:608-611 [Conf]
  4. Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
    Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:730-735 [Conf]
  5. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
    Data Cache Sizing for Embedded Processor Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:925-926 [Conf]
  6. Preeti Ranjan Panda, Nikil D. Dutt
    Memory Architectures for Embedded Systems-On-Chip. [Citation Graph (0, 0)][DBLP]
    HiPC, 2002, pp:647-662 [Conf]
  7. Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri
    A Flexible Scheme for State Assignment Based on Characteristics of the FSM. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:226-229 [Conf]
  8. Preeti Ranjan Panda
    Memory bank customization and assignment in behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:477-481 [Conf]
  9. Preeti Ranjan Panda, Lakshmikantam Chitturi
    An energy-conscious algorithm for memory port allocation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:572-576 [Conf]
  10. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
    Exploiting off-chip memory access modes in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:333-340 [Conf]
  11. Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
    A Data Alignment Technique for Improving Cache Performance. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:587-592 [Conf]
  12. Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
    Improving cache Performance Through Tiling and Data Alignment. [Citation Graph (0, 0)][DBLP]
    IRREGULAR, 1997, pp:167-185 [Conf]
  13. Preeti Ranjan Panda, Nikil D. Dutt
    Low-power mapping of behavioral arrays to multiple memories. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:289-292 [Conf]
  14. Preeti Ranjan Panda
    SystemC. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:75-80 [Conf]
  15. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
    Memory Organization for Improved Data Cache Performance in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:90-95 [Conf]
  16. Preeti Ranjan Panda, Nikil D. Dutt
    1995 high level synthesis design repository. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:170-174 [Conf]
  17. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
    Architectural Exploration and Optimization of Local Memory in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:90-0 [Conf]
  18. Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli
    Cache-efficient memory layout of aggregate data structures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:101-106 [Conf]
  19. Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda
    New design paradigms. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:94- [Conf]
  20. Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran
    Specification and Design of Multi-Million Gate SOCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:18-19 [Conf]
  21. Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda
    Embedded Memories in System Design: Technology, Application, Design and Tools. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:5-6 [Conf]
  22. Preeti Ranjan Panda, Nikil D. Dutt
    Behavioral Array Mapping into Multiport Memories Targeting Low Power. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:268-273 [Conf]
  23. Vikram Singh Saun, Preeti Ranjan Panda
    Extracting Exact Finite State Machines from Behavioral SystemC Descriptions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:280-285 [Conf]
  24. Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
    Power Reduction in VLIW Processor with Compiler Driven Bypass Network. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:233-238 [Conf]
  25. Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
    Customization of Register File Banking Architecture for Low Power. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:239-244 [Conf]
  26. Rahul Jain, Preeti Ranjan Panda
    Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:813-818 [Conf]
  27. Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri
    Estimating the Complexity of Synthesized Designs from FSM Specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:1, pp:30-35 [Journal]
  28. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, Francky Catthoor, Arnout Vandecappelle, Erik Brockmeyer, Chidamber Kulkarni, Eddy de Greef
    Data Memory Organization and Optimizations in Application-Specific Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:3, pp:56-68 [Journal]
  29. Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
    Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:142-149 [Journal]
  30. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
    Incorporating DRAM access modes into high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:96-109 [Journal]
  31. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
    Local memory exploration and optimization in embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:3-13 [Journal]
  32. Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg
    Data and memory optimization techniques for embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:2, pp:149-206 [Journal]
  33. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
    On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:682-704 [Journal]
  34. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
    Memory data organization for improved cache performance in embedded processor applications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:4, pp:384-409 [Journal]
  35. Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda
    The impact of loop unrolling on controller delay in high level synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:391-396 [Conf]
  36. Rahul Jain, Preeti Ranjan Panda
    An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1377-1380 [Conf]
  37. Preeti Ranjan Panda, Nikil D. Dutt
    Low-power memory mapping through reducing address bus activity. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:309-320 [Journal]
  38. Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
    Memory allocation and mapping in high-level synthesis - an integrated approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:928-938 [Journal]

  39. REWIRED - Register Write Inhibition by Resource Dedication. [Citation Graph (, )][DBLP]


  40. Online cache state dumping for processor debug. [Citation Graph (, )][DBLP]


  41. Efficient utilization of scratch-pad memory in embedded processor applications. [Citation Graph (, )][DBLP]


  42. A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. [Citation Graph (, )][DBLP]


  43. Cache aware compression for processor debug support. [Citation Graph (, )][DBLP]


  44. Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. [Citation Graph (, )][DBLP]


  45. Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine. [Citation Graph (, )][DBLP]


  46. Front-End Design Flows for Systems on Chip: An Embedded Tutorial. [Citation Graph (, )][DBLP]


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