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Sagar S. Sabade: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sagar S. Sabade, Hank Walker
    Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:755-760 [Conf]
  2. Sagar S. Sabade, D. M. H. Walker
    Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:381-389 [Conf]
  3. Sagar S. Sabade, D. M. H. Walker
    CROWNE: Current Ratio Outliers with Neighbor Estimator. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:132-139 [Conf]
  4. Sagar S. Sabade, D. M. H. Walker
    Improved wafer-level spatial analysis for I_DDQ limit setting. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:82-91 [Conf]
  5. Sagar S. Sabade, D. M. H. Walker
    Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:755-760 [Conf]
  6. Sagar S. Sabade, D. M. H. Walker
    Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:361-0 [Conf]
  7. Sagar S. Sabade, D. M. H. Walker
    Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:889-894 [Conf]
  8. Sagar S. Sabade, D. M. H. Walker
    Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:81-86 [Conf]
  9. Sagar S. Sabade, D. M. H. Walker
    Use of Multiple IDDQ Test Metrics for Outlier Identification. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:31-38 [Conf]
  10. Sagar S. Sabade, D. M. H. Walker
    On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:65-72 [Conf]
  11. Sagar S. Sabade, D. M. H. Walker
    IDDQ Test: Will It Survive the DSM Challenge? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:8-16 [Journal]
  12. Sagar S. Sabade, Duncan M. Walker
    IC Outlier Identification Using Multiple Test Metrics. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:586-595 [Journal]
  13. Sagar S. Sabade, D. M. H. Walker
    IDDQ data analysis using neighbor current ratios. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:287-294 [Journal]
  14. Sagar S. Sabade, D. M. H. Walker
    IDDX-based test methods: A survey. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:159-198 [Journal]
  15. Sagar S. Sabade, D. M. H. Walker
    Estimation of fault-free leakage current using wafer-level spatial information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:91-94 [Journal]

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