The SCEAS System
Navigation Menu

Search the dblp DataBase


David A. Papa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David A. Papa, Igor L. Markov, Philip Chong
    Utility of the OpenAccess database in academic research. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:440-441 [Conf]
  2. David A. Papa, Saurabh N. Adya, Igor L. Markov
    Constructive benchmarking for placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:113-118 [Conf]
  3. Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov
    Unification of partitioning, placement and floorplanning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:550-557 [Conf]
  4. Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hayward H. Chan, Aaron N. Ng, James F. Lu, Igor L. Markov
    Capo: robust and scalable open-source min-cut floorplacer. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:224-226 [Conf]
  5. Jarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L. Markov
    Satisfying whitespace requirements in top-down placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:206-208 [Conf]
  6. Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov
    Early research experience with OpenAccess gear: an open source development environment for physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:94-100 [Conf]
  7. Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco
    InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:487-494 [Conf]
  8. Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov
    Min-cut floorplacement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1313-1326 [Journal]

  9. Path smoothing via discrete optimization. [Citation Graph (, )][DBLP]

  10. Pyramids: an efficient computational geometry-based approach for timing-driven placement. [Citation Graph (, )][DBLP]

  11. RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. [Citation Graph (, )][DBLP]

  12. Ultra-fast interconnect driven cell cloning for minimizing critical path delay. [Citation Graph (, )][DBLP]

  13. Incremental Verification with Error Detection, Diagnosis, and Visualization. [Citation Graph (, )][DBLP]

Search in 0.109secs, Finished in 0.111secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002