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Jin-Tai Yan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jin-Tai Yan
    Region definition and ordering assignment with the minimization of the number of switchboxes. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Jin-Tai Yan, Shun-Hua Lin
    Timing-constrained congestion-driven global routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:683-686 [Conf]
  3. Jin-Tai Yan
    An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:128-131 [Conf]
  4. Jin-Tai Yan
    An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:100-0 [Conf]
  5. Jin-Tai Yan
    Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:236-0 [Conf]
  6. Jin-Tai Yan
    An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:366-371 [Conf]
  7. Paul-Waie Shew, Jin-Tai Yan, Pei-Yung Hsiao, Yong-Ching Lim
    Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel Routing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:183-186 [Conf]
  8. Jin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu
    Probabilistic congestion prediction in hierarchical quad-grid model. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1350-1353 [Conf]
  9. Jin-Tai Yan, Pei-Yung Hsiao
    Region Definition of Minimizing the Number of Switchboxes and Ordering Assignment. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:105-108 [Conf]
  10. Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen
    Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2219-2222 [Conf]
  11. Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen
    Wiring area optimization in floorplan-aware hierarchical power grids. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1366-1369 [Conf]
  12. Jin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee
    Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1370-1373 [Conf]
  13. Jin-Tai Yan
    A simple yet effective genetic approach for the orientation assignment on cell-based layout. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:33-36 [Conf]
  14. Jin-Tai Yan, Pei-Yung Hsiao
    A new fuzzy-clustering-based approach for two-way circuit partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:359-364 [Conf]
  15. Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen
    Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:147-152 [Conf]
  16. Jin-Tai Yan, Bo-Yi Chiang
    Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:899-906 [Conf]
  17. Jin-Tai Yan, Pei-Yung Hsiao
    A Fuzzy Clustering Algorithm for Graph Bisection. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1994, v:52, n:5, pp:259-263 [Journal]
  18. Jin-Tai Yan
    Routing Space Estimation and Assignment for Macro-Cell Placement. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 1998, v:8, n:4, pp:435-446 [Journal]
  19. Lih-Der Chang, Pei-Yung Hsiao, Jin-Tai Yan, Paul-Waie Shew
    A robust over-the-cell channel router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1592-1599 [Journal]
  20. Jin-Tai Yan
    An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1519-1526 [Journal]
  21. Jin-Tai Yan
    An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:163-171 [Journal]
  22. Jin-Tai Yan, Pei-Yung Hsiao
    Minimizing the number of switchboxes for region definition and ordering assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:336-347 [Journal]
  23. Jin-Tai Yan
    Three-layer bubble-sorting-based nonManhattan channel routing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:726-734 [Journal]
  24. Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu
    Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3395-3398 [Conf]
  25. Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee
    Timing-constrained yield-driven wire sizing for critical area minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  26. Jin-Tai Yan, Kuen-Ming Lin, Yen-Hsiang Chen
    Optimal shielding insertion for inductive noise avoidance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo
    Floorplan-aware decoupling capacitance budgeting on equivalent circuit model. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang
    Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  29. IO connection assignment and RDL routing for flip-chip designs. [Citation Graph (, )][DBLP]


  30. Two-sided single-detour untangling for bus routing. [Citation Graph (, )][DBLP]


  31. Redundant wire insertion for yield improvement. [Citation Graph (, )][DBLP]


  32. RDL pre-assignment routing for flip-chip designs. [Citation Graph (, )][DBLP]


  33. Ordered escape routing via routability-driven pin assignment. [Citation Graph (, )][DBLP]


  34. Resource-constrained timing-driven link insertion for critical delay reduction. [Citation Graph (, )][DBLP]


  35. Width and Timing-Constrained Wire Sizing for Critical Area Minimization. [Citation Graph (, )][DBLP]


  36. Optimal Network Analysis in Hierarchical Power Quad-Grids. [Citation Graph (, )][DBLP]


  37. Printed circuit board routing and package layout codesign. [Citation Graph (, )][DBLP]


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