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Irith Pomeranz: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Irith Pomeranz, Sudhakar M. Reddy
    A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:677-682 [Conf]
  2. Yun Shao, Sudhakar M. Reddy, Irith Pomeranz
    Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:767-772 [Conf]
  3. N. Devtaprasanna, Sudhakar M. Reddy, A. Gunda, P. Krishnamurthy, Irith Pomeranz
    Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:202-207 [Conf]
  4. Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
    On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:467-471 [Conf]
  5. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:82-0 [Conf]
  6. Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy
    Enhanced untestable path analysis using edge graphs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:139-144 [Conf]
  7. Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy
    Test Data Compression Using Don?t-Care Identification and Statistical Encoding. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:67-0 [Conf]
  8. Irith Pomeranz, Sudhakar M. Reddy
    Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:198-203 [Conf]
  9. Irith Pomeranz, Sudhakar M. Reddy
    Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:446-451 [Conf]
  10. Irith Pomeranz, Sudhakar M. Reddy
    Vector-Based Functional Fault Models for Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:41-46 [Conf]
  11. Irith Pomeranz, Sudhakar M. Reddy
    A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:110-115 [Conf]
  12. Irith Pomeranz, Sudhakar M. Reddy
    Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:61-66 [Conf]
  13. Irith Pomeranz, Sudhakar M. Reddy
    A DFT Approach for Path Delay Faults in Interconnected Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:72-77 [Conf]
  14. Irith Pomeranz, Sudhakar M. Reddy
    Test Data Volume Reduction by Test Data Realignment. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:434-439 [Conf]
  15. Irith Pomeranz, Sudhakar M. Reddy
    Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:75-80 [Conf]
  16. Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin
    Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:467- [Conf]
  17. Irith Pomeranz, Sudhakar M. Reddy
    Properties of Maximally Dominating Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:106-111 [Conf]
  18. Irith Pomeranz, Sudhakar M. Reddy
    A Postprocessing Procedure of Test Enrichment for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:448-453 [Conf]
  19. Irith Pomeranz, Sudhakar M. Reddy
    Static compaction for two-pattern test sets. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:222-228 [Conf]
  20. Irith Pomeranz, Sudhakar M. Reddy
    On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:16-21 [Conf]
  21. Irith Pomeranz, Sudhakar M. Reddy
    Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:226-231 [Conf]
  22. Irith Pomeranz, Sudhakar M. Reddy
    On the Compaction of Test Sets Produced by Genetic Optimization. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:4-9 [Conf]
  23. Ilia Polian, Irith Pomeranz, Bernd Becker
    Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:2-14 [Conf]
  24. Irith Pomeranz, Sudhakar M. Reddy
    TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:74-0 [Conf]
  25. Irith Pomeranz
    On Pass/Fail Dictionaries for Scan Circuits . [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:51-56 [Conf]
  26. Irith Pomeranz, W. Kent Fuchs
    A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:486-491 [Conf]
  27. Irith Pomeranz, Sudhakar M. Reddy
    On the feasibility of fault simulation using partial circuit descriptions. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:108-113 [Conf]
  28. Yun Shao, Irith Pomeranz, Sudhakar M. Reddy
    On Generating High Quality Tests for Transition Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:1- [Conf]
  29. Irith Pomeranz, Sudhakar M. Reddy
    Reducing test application time for full scan circuits by the addition of transfer sequences. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:317-322 [Conf]
  30. Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz
    An Efficient Method to Identify Untestable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:233-238 [Conf]
  31. Irith Pomeranz, Sudhakar M. Reddy
    A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:131-136 [Conf]
  32. Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
    Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:178-183 [Conf]
  33. Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
    Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:132-137 [Conf]
  34. Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
    A test pattern ordering algorithm for diagnosis with truncated fail data. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:399-404 [Conf]
  35. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:653-659 [Conf]
  36. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
    Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:102-106 [Conf]
  37. Wei Li, Sudhakar M. Reddy, Irith Pomeranz
    On test generation for transition faults with minimized peak power dissipation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:504-509 [Conf]
  38. Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
    A scan BIST generation method using a markov source and partial bit-fixing. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:554-559 [Conf]
  39. Irith Pomeranz, Sudhakar M. Reddy
    On Static Compaction of Test Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:215-220 [Conf]
  40. Irith Pomeranz
    Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:145-150 [Conf]
  41. Irith Pomeranz
    On the generation of scan-based test sets with reachable states for testing under functional operation conditions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:928-933 [Conf]
  42. Irith Pomeranz
    Scan-BIST based on transition probabilities. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:940-943 [Conf]
  43. Irith Pomeranz
    N-detection under transparent-scan. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:129-134 [Conf]
  44. Irith Pomeranz, Kwang-Ting Cheng
    State Assignment Using Input/Output Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:573-577 [Conf]
  45. Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
    On output response compression in the presence of unknown output values. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:255-258 [Conf]
  46. Irith Pomeranz, Sudhakar M. Reddy
    On diagnosis of pattern-dependent delay faults. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:59-62 [Conf]
  47. Irith Pomeranz, Sudhakar M. Reddy
    An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:156-161 [Conf]
  48. Irith Pomeranz, Sudhakar M. Reddy
    On test data compression and n-detection test sets. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:748-751 [Conf]
  49. Irith Pomeranz, Sudhakar M. Reddy
    On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:341-346 [Conf]
  50. Irith Pomeranz, Sudhakar M. Reddy
    At-Speed Delay Testing of Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:177-181 [Conf]
  51. Irith Pomeranz, Sudhakar M. Reddy
    INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:80-85 [Conf]
  52. Irith Pomeranz, Sudhakar M. Reddy
    Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:358-364 [Conf]
  53. Irith Pomeranz, Sudhakar M. Reddy
    On Improving Fault Diagnosis for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:504-509 [Conf]
  54. Irith Pomeranz, Sudhakar M. Reddy
    On Synthesis-for-Testability of Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:126-132 [Conf]
  55. Irith Pomeranz, Sudhakar M. Reddy
    Fault Simulation under the Multiple Observation Time Approach using Backward Implications. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:608-613 [Conf]
  56. Irith Pomeranz, Sudhakar M. Reddy
    Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:754-759 [Conf]
  57. Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri
    NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:439-445 [Conf]
  58. Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
    Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:583-0 [Conf]
  59. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    Full Scan Fault Coverage With Partial Scan. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:468-472 [Conf]
  60. Irith Pomeranz, Sudhakar M. Reddy
    Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:298-304 [Conf]
  61. Irith Pomeranz, Sudhakar M. Reddy
    Functional Test Generation for Full Scan Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:396-0 [Conf]
  62. Irith Pomeranz, Sudhakar M. Reddy
    Sequence reordering to improve the levels of compaction achievable by static compaction procedures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:214-218 [Conf]
  63. Irith Pomeranz, Sudhakar M. Reddy
    Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:504-508 [Conf]
  64. Irith Pomeranz, Sudhakar M. Reddy
    Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:722-729 [Conf]
  65. Irith Pomeranz, Sudhakar M. Reddy
    A New Approach to Test Generation and Test Compaction for Scan Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11000-11005 [Conf]
  66. Irith Pomeranz, Sudhakar M. Reddy
    Test Data Compression Based on Output Dependence. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11186-11187 [Conf]
  67. Irith Pomeranz, Sudhakar M. Reddy
    Level of Similarity: A Metric for Fault Collapsing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:56-61 [Conf]
  68. Irith Pomeranz, Sudhakar M. Reddy
    Worst-Case and Average-Case Analysis of n-Detection Test Sets. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:444-449 [Conf]
  69. Irith Pomeranz, Sudhakar M. Reddy
    The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1008-1013 [Conf]
  70. Irith Pomeranz, Sudhakar M. Reddy
    Generation of broadside transition fault test sets that detect four-way bridging faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:907-912 [Conf]
  71. Irith Pomeranz, Sudhakar M. Reddy
    Test compaction for transition faults under transparent-scan. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1264-1269 [Conf]
  72. Irith Pomeranz, Sudhakar M. Reddy
    A Synthesis Procedure for Flexible Logic Functions. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:973-974 [Conf]
  73. Irith Pomeranz, Sudhakar M. Reddy
    Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:983-984 [Conf]
  74. Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
    On the Characterization of Hard-to-Detect Bridging Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11012-11019 [Conf]
  75. Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy
    Finding a Common Fault Response for Diagnosis during Silicon Debug. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1116- [Conf]
  76. Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri
    Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:68-75 [Conf]
  77. Irith Pomeranz, Yervant Zorian
    Fault Isolation Using Tests for Non-Isolated Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1123- [Conf]
  78. Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz
    Defect Aware Test Patterns. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:450-455 [Conf]
  79. Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy
    Test Data Compression Using Don't-Care Identification and Statistical Encoding. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:413-416 [Conf]
  80. Irith Pomeranz, Sudhakar M. Reddy
    Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:377-381 [Conf]
  81. Irith Pomeranz, Sudhakar M. Reddy
    Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:183-190 [Conf]
  82. Irith Pomeranz, Sudhakar M. Reddy
    Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:469-476 [Conf]
  83. Irith Pomeranz, Sudhakar M. Reddy
    Recovery During Concurrent On-Line Testing of Identical Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:475-483 [Conf]
  84. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz
    On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:398-405 [Conf]
  85. Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz
    Selecting High-Quality Delay Tests for Manufacturing Test and Debug. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:59-70 [Conf]
  86. N. Devtaprasanna, A. Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
    Test Generation for Open Defects in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:41-49 [Conf]
  87. Irith Pomeranz, Sudhakar M. Reddy
    Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:419-427 [Conf]
  88. Irith Pomeranz, Sudhakar M. Reddy
    Test-Point Insertion to Enhance Test Compaction for Scan Designs. [Citation Graph (0, 0)][DBLP]
    DSN, 2000, pp:375-381 [Conf]
  89. Niraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller
    Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:280-287 [Conf]
  90. Irith Pomeranz, Sudhakar M. Reddy
    Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:52-59 [Conf]
  91. Irith Pomeranz, Sudhakar M. Reddy
    A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:230-237 [Conf]
  92. Irith Pomeranz, Sudhakar M. Reddy
    EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:166-175 [Conf]
  93. Irith Pomeranz, Sudhakar M. Reddy
    Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:492-501 [Conf]
  94. Irith Pomeranz, Sudhakar M. Reddy
    LOCSTEP: A Logic Simulation Based Test Generation Procedure. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:110-119 [Conf]
  95. Irith Pomeranz, Sudhakar M. Reddy
    Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:53-61 [Conf]
  96. Irith Pomeranz, Sudhakar M. Reddy
    ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation. [Citation Graph (0, 0)][DBLP]
    FTCS, 1997, pp:144-151 [Conf]
  97. Irith Pomeranz, Sudhakar M. Reddy
    A Generalized Test Generation Procedure for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    FTCS, 1998, pp:274-283 [Conf]
  98. Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel
    Theory and Practice of Sequential Machine Testing and Testability. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:330-337 [Conf]
  99. Sudhakar M. Reddy, Irith Pomeranz, Rahul Jain
    On Codeword Testing of Two-Rail and Parity TSC Checkers. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:116-125 [Conf]
  100. Prasanti Uppaluri, Irith Pomeranz, Sudhakar M. Reddy
    Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:456-465 [Conf]
  101. Irith Pomeranz, Sudhakar M. Reddy
    ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:13-18 [Conf]
  102. Irith Pomeranz, Sudhakar M. Reddy
    On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:20-25 [Conf]
  103. Irith Pomeranz, Sudhakar M. Reddy
    Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:216-221 [Conf]
  104. Irith Pomeranz, Sudhakar M. Reddy
    PASTA: Partial Scan to Enhance Test Compaction. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:4-7 [Conf]
  105. Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel
    On Double Transition Faults as a Delay Fault Model. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:282-287 [Conf]
  106. Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski
    Improving the Proportion of At-Speed Tests in Scan BIST. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:459-463 [Conf]
  107. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    Techniques for improving the efficiency of sequential circuit test generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:147-151 [Conf]
  108. Irith Pomeranz, Sudhakar M. Reddy
    Simulation Based Test Generation for Scan Designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:544-549 [Conf]
  109. Irith Pomeranz, Sudhakar M. Reddy
    On undetectable faults in partial scan circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:82-86 [Conf]
  110. Irith Pomeranz, Sudhakar M. Reddy
    On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:867-873 [Conf]
  111. Irith Pomeranz, Sudhakar M. Reddy
    Test Generation for Synchronous Sequential Circuits Based on Fault Extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:450-453 [Conf]
  112. Irith Pomeranz, Sudhakar M. Reddy
    On the generation of small dictionaries for fault location. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:272-279 [Conf]
  113. Irith Pomeranz, Sudhakar M. Reddy
    An efficient non-enumerative method to estimate path delay fault coverage. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:560-567 [Conf]
  114. Irith Pomeranz, Sudhakar M. Reddy
    Test generation for path delay faults based on learning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:428-435 [Conf]
  115. Irith Pomeranz, Sudhakar M. Reddy
    On diagnosis and correction of design errors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:500-507 [Conf]
  116. Irith Pomeranz, Sudhakar M. Reddy
    On testing delay faults in macro-based combinational circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:332-339 [Conf]
  117. Irith Pomeranz, Sudhakar M. Reddy
    On error correction in macro-based circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:568-575 [Conf]
  118. Irith Pomeranz, Sudhakar M. Reddy
    Functional test generation for delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:687-694 [Conf]
  119. Irith Pomeranz, Sudhakar M. Reddy
    Built-in test generation for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:421-426 [Conf]
  120. Irith Pomeranz, Sudhakar M. Reddy
    An approach for improving the levels of compaction achieved by vector omission. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:463-466 [Conf]
  121. Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy
    Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:454-457 [Conf]
  122. Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy
    COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:568-574 [Conf]
  123. Paul G. Ryan, W. Kent Fuchs, Irith Pomeranz
    Fault dictionary compression and equivalence class computation for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:508-511 [Conf]
  124. Chen Wang, Irith Pomeranz, Sudhakar M. Reddy
    REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:370-374 [Conf]
  125. Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
    Conflict driven techniques for improving deterministic test pattern generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:87-93 [Conf]
  126. Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer
    On Compacting Test Response Data Containing Unknown Values. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:855-862 [Conf]
  127. Irith Pomeranz, Sudhakar M. Reddy
    A delay fault model for at-speed fault simulation and test generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:89-95 [Conf]
  128. Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
    A Low Power Pseudo-Random BIST Technique. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:468-473 [Conf]
  129. Gang Chen, Sudhakar M. Reddy, Irith Pomeranz
    Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:36-41 [Conf]
  130. N. Devtaprasanna, A. Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
    A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:471-474 [Conf]
  131. Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
    A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:397-0 [Conf]
  132. Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy
    Don't-Care Identification on Specific Bits of Test Patterns. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:194-199 [Conf]
  133. Irith Pomeranz, Sudhakar M. Reddy
    A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:148-153 [Conf]
  134. Irith Pomeranz, Sudhakar M. Reddy
    On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:206-209 [Conf]
  135. Irith Pomeranz, Sudhakar M. Reddy
    Static Test Compaction for Multiple Full-Scan Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:393-396 [Conf]
  136. Irith Pomeranz, Sudhakar M. Reddy
    On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:82-84 [Conf]
  137. Irith Pomeranz, Sudhakar M. Reddy
    Test generation for multiple state-table faults in finite-state machines. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:292-0 [Conf]
  138. Irith Pomeranz, Sudhakar M. Reddy
    Fault Location based on Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:154-0 [Conf]
  139. Irith Pomeranz, Sudhakar M. Reddy
    Fault Location Based on Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:242-247 [Conf]
  140. Irith Pomeranz, Sudhakar M. Reddy
    Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:360-365 [Conf]
  141. Irith Pomeranz, Sudhakar M. Reddy
    Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:412-417 [Conf]
  142. Irith Pomeranz, Sudhakar M. Reddy
    Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:389-394 [Conf]
  143. Irith Pomeranz, Sudhakar M. Reddy
    On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:395-0 [Conf]
  144. Irith Pomeranz, Sudhakar M. Reddy
    COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:142-147 [Conf]
  145. Irith Pomeranz, Sudhakar M. Reddy
    Testing of Fault-Tolerant Hardware. [Citation Graph (0, 0)][DBLP]
    Fault-Tolerant Computing Systems, 1991, pp:148-159 [Conf]
  146. Venkataramana Kommu, Irith Pomeranz
    Effect of Communication in a Parallel Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1992, pp:310-317 [Conf]
  147. Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
    A Low Power Pseudo-Random BIST Technique. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:140-0 [Conf]
  148. Chaowen Yu, Wei Li, Sudhakar M. Reddy, Irith Pomeranz
    An Improved Markov Source Design for Scan BIST. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:106-110 [Conf]
  149. Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz
    A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:37-42 [Conf]
  150. Mohamed Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar
    Transient-Fault Recovery for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:98-109 [Conf]
  151. T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
    Transient-Fault Recovery Using Simultaneous Multithreading. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:87-98 [Conf]
  152. Yuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi
    Battery-aware dynamic voltage scaling in multiprocessor embedded system. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:616-619 [Conf]
  153. Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy
    Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:211-216 [Conf]
  154. Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy
    Scan BIST Targeting Transition Faults Using a Markov Source. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:497-502 [Conf]
  155. Irith Pomeranz, Sudhakar M. Reddy
    Dynamic Test Compaction for Bridging Faults. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:250-255 [Conf]
  156. Wei Li, Sudhakar M. Reddy, Irith Pomeranz
    On Reducing Peak Current and Power during Test. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:156-161 [Conf]
  157. Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy
    Fault Diagnosis and Fault Model Aliasing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:206-211 [Conf]
  158. Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz
    Pseudo Random Patterns Using Markov Sources for Scan BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1013-1021 [Conf]
  159. Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy
    On static test compaction and test pattern ordering for scan designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1088-1097 [Conf]
  160. Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
    On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1060-1068 [Conf]
  161. Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy
    Selection of potentially testable path delay faults for test generation. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:376-384 [Conf]
  162. Irith Pomeranz
    Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:441-450 [Conf]
  163. Irith Pomeranz, Sudhakar M. Reddy
    A method to enhance the fault coverage obtained by output response comparison of identical circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:196-203 [Conf]
  164. Irith Pomeranz, Sudhakar M. Reddy
    On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:211-220 [Conf]
  165. Irith Pomeranz, Sudhakar M. Reddy
    Achieving Complete Delay Fault Testability by Extra Inputs. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:273-282 [Conf]
  166. Irith Pomeranz, Sudhakar M. Reddy
    A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:998-1007 [Conf]
  167. Irith Pomeranz, Sudhakar M. Reddy
    On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:1007-1016 [Conf]
  168. Irith Pomeranz, Sudhakar M. Reddy
    Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:272-281 [Conf]
  169. Irith Pomeranz, Sudhakar M. Reddy
    On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:357-366 [Conf]
  170. Irith Pomeranz, Sudhakar M. Reddy
    A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1074-1083 [Conf]
  171. Irith Pomeranz, Sudhakar M. Reddy
    On achieving complete coverage of delay faults in full scan circuits using locally available lines. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:923-931 [Conf]
  172. Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
    COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:194-203 [Conf]
  173. Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li
    Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:904-913 [Conf]
  174. Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy
    Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:489-497 [Conf]
  175. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta
    On validating data hold times for flip-flops in sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:317-325 [Conf]
  176. Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
    On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:83-89 [Conf]
  177. Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz
    On Potential Fault Detection in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:142-149 [Conf]
  178. Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    The effects of test compaction on fault diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1083-1089 [Conf]
  179. Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz
    On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1079-1088 [Conf]
  180. Irith Pomeranz, Sudhakar M. Reddy
    Fault diagnosis based on parameters of output responses. [Citation Graph (0, 0)][DBLP]
    PRDC, 2000, pp:139-147 [Conf]
  181. Wei Zou, C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz
    Optimizing SOC Test Resources using Dual Sequences. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:180-185 [Conf]
  182. Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
    New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:419-424 [Conf]
  183. Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
    On Improving Static Test Compaction for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:111-116 [Conf]
  184. Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
    Test Transformation to Improve Compaction by Statistical Encoding. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:294-299 [Conf]
  185. Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
    A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:82-87 [Conf]
  186. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    MIX: A Test Generation System for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:456-463 [Conf]
  187. Irith Pomeranz, Sudhakar M. Reddy
    On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:392-397 [Conf]
  188. Irith Pomeranz, Sudhakar M. Reddy
    A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:677-682 [Conf]
  189. Irith Pomeranz, Sudhakar M. Reddy
    Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:335-340 [Conf]
  190. Irith Pomeranz, Sudhakar M. Reddy
    On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:741-744 [Conf]
  191. Irith Pomeranz, Sudhakar M. Reddy
    Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:41-46 [Conf]
  192. Irith Pomeranz, Sudhakar M. Reddy
    The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:828-831 [Conf]
  193. Irith Pomeranz, Sudhakar M. Reddy
    On the Generation of Weights for Weighted Pseudo Random Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:69-72 [Conf]
  194. Irith Pomeranz, Sudhakar M. Reddy
    On Determining Symmetries in Inputs of Logic Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:255-260 [Conf]
  195. Irith Pomeranz, Sudhakar M. Reddy
    On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:254-259 [Conf]
  196. Irith Pomeranz, Sudhakar M. Reddy
    On the Detection of Reset Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:470-474 [Conf]
  197. Irith Pomeranz, Sudhakar M. Reddy
    On Full Reset as a Design-For-Testability Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:534-536 [Conf]
  198. Irith Pomeranz, Sudhakar M. Reddy
    On Test Compaction Objectives for Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:279-284 [Conf]
  199. Irith Pomeranz, Sudhakar M. Reddy
    VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:250-255 [Conf]
  200. Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Enamul Amyeen
    Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:475-480 [Conf]
  201. Yun Shao, Irith Pomeranz, Sudhakar M. Reddy
    Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:767-772 [Conf]
  202. Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz
    GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:533-538 [Conf]
  203. Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz
    On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:59-64 [Conf]
  204. Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy
    MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:110-115 [Conf]
  205. Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
    Low Shift and Capture Power Scan Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:793-798 [Conf]
  206. Irith Pomeranz, Sudhakar M. Reddy
    Functional Broadside Tests with Different Levels of Reachability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:799-804 [Conf]
  207. Irith Pomeranz, Sudhakar M. Reddy
    Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:498-503 [Conf]
  208. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
    Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:124-130 [Conf]
  209. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
    Implication and Evaluation Techniques for Proving Fault Equivalence. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:201-213 [Conf]
  210. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs
    Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:181-186 [Conf]
  211. Yuan Lu, Irith Pomeranz
    Synchronization of large sequential circuits by partial reset. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:93-98 [Conf]
  212. Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
    A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:260-267 [Conf]
  213. Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy
    A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:294-299 [Conf]
  214. Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy
    SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:205-212 [Conf]
  215. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    On Removing Redundant Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:168-175 [Conf]
  216. Irith Pomeranz, Sudhakar M. Reddy
    On the Use of Fault Dominance in n-Detection Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:352-357 [Conf]
  217. Irith Pomeranz, Sudhakar M. Reddy
    On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:173-178 [Conf]
  218. Irith Pomeranz, Sudhakar M. Reddy
    EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:329-335 [Conf]
  219. Irith Pomeranz, Sudhakar M. Reddy
    On n-detection test sequences for synchronous sequential circuits343. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:336-343 [Conf]
  220. Irith Pomeranz, Sudhakar M. Reddy
    On Synchronizing Sequences and Test Sequence Partitioning. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:158-167 [Conf]
  221. Irith Pomeranz, Sudhakar M. Reddy
    Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:289-295 [Conf]
  222. Irith Pomeranz, Sudhakar M. Reddy
    A Flexible Path Selection Procedure for Path Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:152-159 [Conf]
  223. Irith Pomeranz, Sudhakar M. Reddy
    On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:173-181 [Conf]
  224. Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian
    A Test Interface for Built-In Test of Non-Isolated Scanned Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:371-378 [Conf]
  225. Irith Pomeranz, Yervant Zorian
    Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:41-48 [Conf]
  226. Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
    On Test Data Volume Reduction for Multiple Scan Chain Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:103-110 [Conf]
  227. Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin
    Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:275-283 [Conf]
  228. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
    On the effects of test compaction on defect coverage. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:430-437 [Conf]
  229. Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara
    Compact test generation for bridging faults under I/sub DDQ/ testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:310-316 [Conf]
  230. Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy
    Dominance Based Analysis for Large Volume Production Fail Diagnosis. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:392-399 [Conf]
  231. Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz
    On minimizing the number of test points needed to achieve complete robust path delay fault testability. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:288-295 [Conf]
  232. Xiaoming Yu, Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz
    Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:351-358 [Conf]
  233. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
    Scan Tests with Multiple Fault Activation Cycles for Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:343-348 [Conf]
  234. Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang
    SOC Test Scheduling Using Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:325-330 [Conf]
  235. Irith Pomeranz, Sudhakar M. Reddy
    Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:416-421 [Conf]
  236. Irith Pomeranz, Sudhakar M. Reddy
    On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:174, n:4, pp:83-93 [Journal]
  237. Irith Pomeranz, Sudhakar M. Reddy
    Delay fault models for VLSI circuits1. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:21-40 [Journal]
  238. Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz
    Transient-Fault Recovery for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:76-83 [Journal]
  239. Irith Pomeranz, Zvi Kohavi
    Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:11, pp:1198-1214 [Journal]
  240. Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
    Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:1, pp:83-88 [Journal]
  241. Irith Pomeranz, Sudhakar M. Reddy
    On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:1, pp:88-94 [Journal]
  242. Irith Pomeranz, Sudhakar M. Reddy
    On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:2, pp:175-181 [Journal]
  243. Irith Pomeranz, Sudhakar M. Reddy
    Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:6, pp:596-607 [Journal]
  244. Irith Pomeranz, Sudhakar M. Reddy
    Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:4, pp:409-419 [Journal]
  245. Irith Pomeranz, Sudhakar M. Reddy
    Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:7, pp:866-872 [Journal]
  246. Irith Pomeranz, Sudhakar M. Reddy
    A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:11, pp:1282-1293 [Journal]
  247. Irith Pomeranz, Sudhakar M. Reddy
    On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:9, pp:1121-1133 [Journal]
  248. Irith Pomeranz, Sudhakar M. Reddy
    A Measure of Quality for n-Detection Test Sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1497-1503 [Journal]
  249. Irith Pomeranz, Sudhakar M. Reddy
    Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:12, pp:1569-1581 [Journal]
  250. Irith Pomeranz, Sudhakar M. Reddy
    On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:4, pp:491-495 [Journal]
  251. Irith Pomeranz, Sudhakar M. Reddy
    The Multiple Observation Time Test Strategy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:5, pp:627-637 [Journal]
  252. Irith Pomeranz, Sudhakar M. Reddy
    Classification of Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1066-1077 [Journal]
  253. Irith Pomeranz, Sudhakar M. Reddy
    Testing of Fault-Tolerant Hardware Through Partial Control of Inputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:10, pp:1267-1271 [Journal]
  254. Irith Pomeranz, Sudhakar M. Reddy
    Application of Homing Sequences to Synchronous Sequential Circuit Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:5, pp:569-580 [Journal]
  255. Irith Pomeranz, Sudhakar M. Reddy
    On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:9, pp:1100-1105 [Journal]
  256. Irith Pomeranz, Sudhakar M. Reddy
    Aliasing Computation Using Fault Simulation with Fault Dropping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:1, pp:139-144 [Journal]
  257. Irith Pomeranz, Sudhakar M. Reddy
    On Fault Simulation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:2, pp:335-340 [Journal]
  258. Irith Pomeranz, Sudhakar M. Reddy
    INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:6, pp:792-804 [Journal]
  259. Irith Pomeranz, Sudhakar M. Reddy
    On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:20-32 [Journal]
  260. Irith Pomeranz, Sudhakar M. Reddy
    On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:50-62 [Journal]
  261. Irith Pomeranz, Sudhakar M. Reddy
    On Dictionary-Based Fault Location in Digital Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:1, pp:48-59 [Journal]
  262. Irith Pomeranz, Sudhakar M. Reddy
    Test Generation for Multiple State-Table Faults in Finite-State Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:7, pp:783-794 [Journal]
  263. Irith Pomeranz, Sudhakar M. Reddy
    Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:10, pp:1124-1135 [Journal]
  264. Irith Pomeranz, Sudhakar M. Reddy
    A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:10, pp:1145-1152 [Journal]
  265. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
    Fault equivalence identification in combinational circuits using implication and evaluation techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:922-936 [Journal]
  266. Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy
    On reducing test application time for scan circuits using limited scan operations and transfer sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1594-1605 [Journal]
  267. Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy
    Techniques for minimizing power dissipation in scan and combinational circuits during test application. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1325-1333 [Journal]
  268. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    Reverse-order-restoration-based static test compaction for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:293-304 [Journal]
  269. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    PROPTEST: a property-based test generator for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1080-1091 [Journal]
  270. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
    Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1496-1504 [Journal]
  271. Irith Pomeranz
    On the use of random limited-scan to improve at-speed randompattern testing of scan circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1068-1076 [Journal]
  272. Irith Pomeranz
    Constrained test generation for embedded synchronous sequential circuits with serial-input access. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:164-172 [Journal]
  273. Irith Pomeranz
    Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:10, pp:1465-1478 [Journal]
  274. Irith Pomeranz, Kwang-Ting Cheng
    STOIC: state assignment based on output/input functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1123-1131 [Journal]
  275. Irith Pomeranz, Zvi Kohavi
    A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:247-259 [Journal]
  276. Irith Pomeranz, Sudhakar M. Reddy
    On n-detection test sets and variable n-detection test sets fortransition faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:3, pp:372-383 [Journal]
  277. Irith Pomeranz, Sudhakar M. Reddy
    A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:589-600 [Journal]
  278. Irith Pomeranz, Sudhakar M. Reddy
    On synchronizable circuits and their synchronizing sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1086-1092 [Journal]
  279. Irith Pomeranz, Sudhakar M. Reddy
    Vector replacement to improve static-test compaction forsynchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:336-342 [Journal]
  280. Irith Pomeranz, Sudhakar M. Reddy
    On diagnosis and diagnostic test generation for pattern-dependenttransition faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:791-800 [Journal]
  281. Irith Pomeranz, Sudhakar M. Reddy
    Forward-looking fault simulation for improved static compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1262-1265 [Journal]
  282. Irith Pomeranz, Sudhakar M. Reddy
    Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:628-637 [Journal]
  283. Irith Pomeranz, Sudhakar M. Reddy
    Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:706-714 [Journal]
  284. Irith Pomeranz, Sudhakar M. Reddy
    n-pass n-detection fault simulation and its applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:980-986 [Journal]
  285. Irith Pomeranz, Sudhakar M. Reddy
    Test enrichment for path delay faults using multiple sets of target faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:82-90 [Journal]
  286. Irith Pomeranz, Sudhakar M. Reddy
    Theorems for identifying undetectable faults in partial-scan circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1092-1097 [Journal]
  287. Irith Pomeranz, Sudhakar M. Reddy
    Test data compression based on input-output dependence. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1450-1455 [Journal]
  288. Irith Pomeranz, Sudhakar M. Reddy
    Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:12, pp:1663-1670 [Journal]
  289. Irith Pomeranz, Sudhakar M. Reddy
    Vector-restoration-based static compaction using random initial omission. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1587-1592 [Journal]
  290. Irith Pomeranz, Sudhakar M. Reddy
    On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:288-294 [Journal]
  291. Irith Pomeranz, Sudhakar M. Reddy
    On fault equivalence, fault dominance, and incompletely specified test sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1271-1274 [Journal]
  292. Irith Pomeranz, Sudhakar M. Reddy
    Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:591-596 [Journal]
  293. Irith Pomeranz, Sudhakar M. Reddy
    Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1170-1175 [Journal]
  294. Irith Pomeranz, Sudhakar M. Reddy
    Generation of Functional Broadside Tests for Transition Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2207-2218 [Journal]
  295. Irith Pomeranz, Sudhakar M. Reddy
    Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2219-2227 [Journal]
  296. Irith Pomeranz, Sudhakar M. Reddy
    Improved n-Detection Test Sequences Under Transparent Scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2492-2501 [Journal]
  297. Irith Pomeranz, Sudhakar M. Reddy
    3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1050-1058 [Journal]
  298. Irith Pomeranz, Sudhakar M. Reddy
    An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:240-250 [Journal]
  299. Irith Pomeranz, Sudhakar M. Reddy
    SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:251-263 [Journal]
  300. Irith Pomeranz, Sudhakar M. Reddy
    On achieving complete fault coverage for sequential machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:3, pp:378-386 [Journal]
  301. Irith Pomeranz, Sudhakar M. Reddy
    On determining symmetries in inputs of logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:11, pp:1428-1434 [Journal]
  302. Irith Pomeranz, Sudhakar M. Reddy
    On correction of multiple design errors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:255-264 [Journal]
  303. Irith Pomeranz, Sudhakar M. Reddy
    LOCSTEP: a logic-simulation-based test generation procedure. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:544-554 [Journal]
  304. Irith Pomeranz, Sudhakar M. Reddy
    On error correction in macro-based circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1088-1100 [Journal]
  305. Irith Pomeranz, Sudhakar M. Reddy
    Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:269-278 [Journal]
  306. Irith Pomeranz, Sudhakar M. Reddy
    Design-for-testability for path delay faults in large combinational circuits using test points. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:333-343 [Journal]
  307. Irith Pomeranz, Sudhakar M. Reddy
    Test sequences to achieve high defect coverage for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:1017-1029 [Journal]
  308. Irith Pomeranz, Sudhakar M. Reddy
    A comment on "Improving a nonenumerative method to estimate path delay fault coverage". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:665-666 [Journal]
  309. Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo
    Static test compaction for synchronous sequential circuits based on vector restoration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1040-1049 [Journal]
  310. Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
    On the characterization and efficient computation of hard-to-detect bridging faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1640-1649 [Journal]
  311. Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy
    COMPACTEST: a method to generate compact test sets for combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1040-1049 [Journal]
  312. Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri
    NEST: a nonenumerative test generation method for path delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1505-1515 [Journal]
  313. Irith Pomeranz, Y. Zonan
    Testing of scan circuits containing nonisolated random-logic legacycores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:980-993 [Journal]
  314. Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
    Compact test sets for high defect coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:923-930 [Journal]
  315. Irith Pomeranz, Sudhakar M. Reddy
    Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Dependable Sec. Comput., 2005, v:2, n:3, pp:190-200 [Journal]
  316. Irith Pomeranz, Sudhakar M. Reddy
    Functional test generation for delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:231-248 [Journal]
  317. Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
    On test data volume reduction for multiple scan chain designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:460-469 [Journal]
  318. Irith Pomeranz, Sudhakar M. Reddy
    Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:780-788 [Journal]
  319. Irith Pomeranz, Sudhakar M. Reddy
    Autoscan: a scan design without external scan inputs or outputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1087-1095 [Journal]
  320. Irith Pomeranz, Yervant Zorian
    Fault isolation for nonisolated blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1385-1388 [Journal]
  321. Irith Pomeranz, Sudhakar M. Reddy
    On test generation by input cube avoidance. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:522-527 [Conf]
  322. Irith Pomeranz, Sudhakar M. Reddy
    Fault Collapsing for Transition Faults Using Extended Transition Faults. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:173-178 [Conf]
  323. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi
    Enhancing Delay Fault Coverage through Low Power Segmented Scan. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:21-28 [Conf]
  324. Irith Pomeranz, Sudhakar M. Reddy
    Diagnostic Test Generation Based on Subsets of Faults. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:151-158 [Conf]
  325. N. Devtaprasanna, A. Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
    A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:185-192 [Conf]
  326. Irith Pomeranz, Sudhakar M. Reddy
    The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  327. Irith Pomeranz, Sudhakar M. Reddy
    Worst-Case and Average-Case Analysis of n-Detection Test Sets [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  328. Irith Pomeranz, Sudhakar M. Reddy
    Forming N-detection test sets without test generation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]
  329. Irith Pomeranz, Sudhakar M. Reddy
    On methods to match a test pattern generator to a circuit-under-test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:432-444 [Journal]
  330. Irith Pomeranz, Sudhakar M. Reddy
    A built-in self-test method for diagnosis of synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:290-296 [Journal]
  331. Irith Pomeranz, Sudhakar M. Reddy
    Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:679-689 [Journal]

  332. Dynamic test compaction for a random test generation procedure with input cube avoidance. [Citation Graph (, )][DBLP]


  333. Detectability of internal bridging faults in scan chains. [Citation Graph (, )][DBLP]


  334. Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. [Citation Graph (, )][DBLP]


  335. Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. [Citation Graph (, )][DBLP]


  336. Test vector chains for increased targeted and untargeted fault coverage. [Citation Graph (, )][DBLP]


  337. N-distinguishing Tests for Enhanced Defect Diagnosis. [Citation Graph (, )][DBLP]


  338. Fault Diagnosis under Transparent-Scan. [Citation Graph (, )][DBLP]


  339. On tests to detect via opens in digital CMOS circuits. [Citation Graph (, )][DBLP]


  340. A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution. [Citation Graph (, )][DBLP]


  341. On the use of reset to increase the testability of interconnected finite-state machines. [Citation Graph (, )][DBLP]


  342. A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. [Citation Graph (, )][DBLP]


  343. On improving genetic optimization based test generation. [Citation Graph (, )][DBLP]


  344. Selection of a fault model for fault diagnosis based on unique responses. [Citation Graph (, )][DBLP]


  345. A scalable method for the generation of small test sets. [Citation Graph (, )][DBLP]


  346. On reset based functional broadside tests. [Citation Graph (, )][DBLP]


  347. Reducing the storage requirements of a test sequence by using a background vector. [Citation Graph (, )][DBLP]


  348. A-Diagnosis: A Complement to Z-Diagnosis. [Citation Graph (, )][DBLP]


  349. Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. [Citation Graph (, )][DBLP]


  350. On-chip Generation of the Second Primary Input Vectors of Broadside Tests. [Citation Graph (, )][DBLP]


  351. ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. [Citation Graph (, )][DBLP]


  352. Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. [Citation Graph (, )][DBLP]


  353. On Reducing Circuit Malfunctions Caused by Soft Errors. [Citation Graph (, )][DBLP]


  354. Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences. [Citation Graph (, )][DBLP]


  355. Improving the Detectability of Resistive Open Faults in Scan Cells. [Citation Graph (, )][DBLP]


  356. On generating compact test sequences for synchronous sequential circuits. [Citation Graph (, )][DBLP]


  357. Partitioned n-detection test generation. [Citation Graph (, )][DBLP]


  358. Definition and application of approximate necessary assignments. [Citation Graph (, )][DBLP]


  359. State persistence: a property for guiding test generation. [Citation Graph (, )][DBLP]


  360. Deterministic broadside test generation for transition path delay faults. [Citation Graph (, )][DBLP]


  361. An Enhanced Logic BIST Architecture for Online Testing. [Citation Graph (, )][DBLP]


  362. On Common-Mode Skewed-Load and Broadside Tests. [Citation Graph (, )][DBLP]


  363. Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. [Citation Graph (, )][DBLP]


  364. Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. [Citation Graph (, )][DBLP]


  365. The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. [Citation Graph (, )][DBLP]


  366. Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. [Citation Graph (, )][DBLP]


  367. Output-Dependent Diagnostic Test Generation. [Citation Graph (, )][DBLP]


  368. Synthesis for Broadside Testability of Transition Faults. [Citation Graph (, )][DBLP]


  369. Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. [Citation Graph (, )][DBLP]


  370. On the Detectability of Scan Chain Internal Faults — An Industrial Case Study. [Citation Graph (, )][DBLP]


  371. Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation. [Citation Graph (, )][DBLP]


  372. Input test data volume reduction based on test vector chains. [Citation Graph (, )][DBLP]


  373. Scan-Based Tests with Low Switching Activity. [Citation Graph (, )][DBLP]


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