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Title:
Author:
Erich Barke: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Silke Salewski, Erich Barke
    An Upper Bound for 3D Slicing Floorplans. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:567-572 [Conf]
  2. Reza Sedaghat-Maman, Erich Barke
    Real Time Fault Injection Using Logic Emulators. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:475-479 [Conf]
  3. Walter Hartong, Lars Hedrich, Erich Barke
    On Discrete Modeling and Model Checking for Nonlinear Analog Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 2002, pp:401-413 [Conf]
  4. Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke
    A current driven routing and verification methodology for analog applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:385-389 [Conf]
  5. Carsten Borchers, Lars Hedrich, Erich Barke
    Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:236-239 [Conf]
  6. Walter Hartong, Lars Hedrich, Erich Barke
    Model checking algorithms for analog verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:542-547 [Conf]
  7. Erich Barke
    Resistance calculation from mask artwork data by finite element method. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:305-311 [Conf]
  8. Joerg Abke, Erich Barke
    A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1085- [Conf]
  9. Thorsten Adler, Erich Barke
    Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:446-450 [Conf]
  10. Walter Hartong, Lars Hedrich, Erich Barke
    An Approach to Model Checking for Nonlinear Analog Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1080- [Conf]
  11. Lars Hedrich, Erich Barke
    A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:649-0 [Conf]
  12. Joachim Küter, Erich Barke
    Architecture driven partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:479-487 [Conf]
  13. Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke
    Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:442-447 [Conf]
  14. Markus Olbrich, Erich Barke
    Placement Using a Localization Probability Model (LPM). [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1412- [Conf]
  15. Markus Olbrich, Achim Rein, Erich Barke
    An improved hierarchical classification algorithm for structural analysis of integrated circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:807- [Conf]
  16. Rolf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke
    Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:274-278 [Conf]
  17. Matthias Ringe, Thomas Lindenkreuz, Erich Barke
    Static Timing Analysis Taking Crosstalk into Account. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:451-0 [Conf]
  18. Matthias Ringe, Thomas Lindenkreuz, Erich Barke
    Path Verification Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:965-966 [Conf]
  19. Joerg Abke, Erich Barke
    CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:191-200 [Conf]
  20. Joerg Abke, Erich Barke
    A New Placement Method for Direct Mapping into LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:27-36 [Conf]
  21. Klaus Harbich, Erich Barke
    PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:133-141 [Conf]
  22. Jörn Stohmann, Erich Barke
    A Universal CLA Adder Generator for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:44-54 [Conf]
  23. Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke
    An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:79-88 [Conf]
  24. Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl
    Robust wiring networks for DfY considering timing constraints. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:43-48 [Conf]
  25. Dirk Behrens, Klaus Harbich, Erich Barke
    Hierarchical partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:470-477 [Conf]
  26. Lars Hedrich, Erich Barke
    A formal approach to nonlinear analog circuit verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:123-127 [Conf]
  27. Andreas C. Lemke, Lars Hedrich, Erich Barke
    Analog circuit sizing based on formal methods using affine arithmetic. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:486-489 [Conf]
  28. Jörn Stohmann, Erich Barke
    A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:489-495 [Conf]
  29. Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten
    Routing of analog busses with parasitic symmetry. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:14-19 [Conf]
  30. Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch
    CHIPDESIGN - A Novel Project-oriented Microelectronics Course. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:71-72 [Conf]
  31. Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel
    PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:306-315 [Conf]
  32. Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke
    Wirelength Reduction Using 3-D Physical Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:453-462 [Conf]
  33. Joerg Abke, Erich Barke, Jörn Stohmann
    A Universal Module Generator for LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:230-235 [Conf]
  34. Klaus Harbich, Jörn Stohmann, Erich Barke, Ludwig Schwoerer
    A Case Study: Logic Emulation - Pitfalls and Solutions. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:160-0 [Conf]
  35. Andreas Hermann, Markus Olbrich, Erich Barke
    Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:13-18 [Conf]
  36. Silke Salewski, Erich Barke
    An Upper Bound for 3D Slicing Floorplans. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:567-572 [Conf]
  37. Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke
    Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:153, n:3, pp:37-52 [Journal]
  38. Erich Barke
    Line-to-ground capacitance calculation for VLSI: a comparison. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:2, pp:295-298 [Journal]
  39. Erich Barke
    FERKEL: Technologieunabhängiges direktivengesteuertes Programmsystem zur Entwurfsregelnprüfung. [Citation Graph (0, 0)][DBLP]
    Angewandte Informatik, 1985, v:27, n:8, pp:328-333 [Journal]
  40. Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke
    Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:706-711 [Conf]
  41. M. Zhang, M. Olbrich, D. Seider, M. Frerichs, H. Kinzelbach, E. Barke
    CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:243-248 [Conf]
  42. Jan Torben Weinkopf, Klaus Harbich, Erich Barke
    Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  43. D. Grabowski, C. Grimm, E. Barke
    Semi-symbolic modeling and simulation of circuits and systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  44. Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten
    Algorithms for automatic length compensation of busses in analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:159-166 [Conf]

  45. Analog circuit simulation using range arithmetics. [Citation Graph (, )][DBLP]


  46. Distribution arithmetic for stochastical analysis. [Citation Graph (, )][DBLP]


  47. Determining the Technical Complexity of Integrated Circuits. [Citation Graph (, )][DBLP]


  48. Formal approaches to analog circuit verification. [Citation Graph (, )][DBLP]


  49. A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. [Citation Graph (, )][DBLP]


  50. Incremental Fault Emulation. [Citation Graph (, )][DBLP]


  51. Considering possible opens in non-tree topology wire delay calculation. [Citation Graph (, )][DBLP]


  52. Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). [Citation Graph (, )][DBLP]


  53. Using Sequential Equations to Improve Efficiency and Robustness. [Citation Graph (, )][DBLP]


  54. Range Arithmetics to Speed up Reachability Analysis of Analog Systems. [Citation Graph (, )][DBLP]


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