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Ajit Pal:
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Publications of Author
- Debasis Samanta, Ajit Pal
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:193-198 [Conf]
- Debasis Samanta, Ajit Pal, Nishant Sinha
Synthesis of High Performance Low Power Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:99-104 [Conf]
- Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya
On finding the minimum test set of a BDD-based circuit. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2006, pp:169-172 [Conf]
- Ajit Pal, Umesh Patel
Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks. [Citation Graph (0, 0)][DBLP] IWDC, 2004, pp:391-396 [Conf]
- Maitrali Marik, Ajit Pal
Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. [Citation Graph (0, 0)][DBLP] VLSI Design, 2004, pp:73-78 [Conf]
- Rajat K. Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal
A general graph theoretic framework for multi-layer channel routing. [Citation Graph (0, 0)][DBLP] VLSI Design, 1995, pp:202-207 [Conf]
- Rajat K. Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal
Computing area and wire length efficient routes for channels. [Citation Graph (0, 0)][DBLP] VLSI Design, 1995, pp:196-201 [Conf]
- Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal
An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing. [Citation Graph (0, 0)][DBLP] VLSI Design, 1997, pp:531-533 [Conf]
- Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta
NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic. [Citation Graph (0, 0)][DBLP] VLSI Design, 1993, pp:80-83 [Conf]
- Debasis Samanta, Ajit Pal
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. [Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:193-198 [Conf]
- Debasis Samanta, Ajit Pal
Synthesis of Dual-VT Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP] VLSI Design, 2003, pp:303-308 [Conf]
- Debasis Samanta, Ajit Pal
Synthesis of Low Power High Performance Dual-VT PTL Circuits. [Citation Graph (0, 0)][DBLP] VLSI Design, 2004, pp:85-0 [Conf]
- Debasis Samanta, Nishant Sinha, Ajit Pal
Synthesis of High Performance Low Power Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:99-104 [Conf]
- Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. [Citation Graph (0, 0)][DBLP] VLSI Design, 2001, pp:227-0 [Conf]
- Akepati Sravan, Sujan Kundu, Ajit Pal
Low Power Sensor Node for a Wireless Sensor Network. [Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:445-450 [Conf]
- Rajat K. Pal, Sudebkumar Prasant Pal, Ajit Pal
An algorithm for finding a non-trivial lower bound for channel routing1. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:25, n:1, pp:71-84 [Journal]
- Ajit Pal
An Algorithm for Optimal Logic Design Using Multiplexers. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1986, v:35, n:8, pp:755-757 [Journal]
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. [Citation Graph (, )][DBLP]
Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations? [Citation Graph (, )][DBLP]
Synthesis & Testing for Low Power. [Citation Graph (, )][DBLP]
Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning. [Citation Graph (, )][DBLP]
Credit Reputation Propagation: A Strategy to Curb Free-Riding in a Large BitTorrent Swarm. [Citation Graph (, )][DBLP]
Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. [Citation Graph (, )][DBLP]
A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks. [Citation Graph (, )][DBLP]
A power-aware wireless sensor network based bridge monitoring system. [Citation Graph (, )][DBLP]
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