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Andrzej J. Strojwas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrzej J. Strojwas
    Design for manufacturability: a path from system level to high yielding chips: embedded tutorial. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:375-376 [Conf]
  2. Jacques Benkoski, Andrzej J. Strojwas
    Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:668-673 [Conf]
  3. Jacques Benkoski, Andrzej J. Strojwas
    The Role of Timing Verification in Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:612-619 [Conf]
  4. Marko P. Chew, Andrzej J. Strojwas
    Utilizing Logic Information in Multi-Level Timing Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:215-218 [Conf]
  5. V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi
    Design methodology for IC manufacturability based on regular logic-bricks. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:353-358 [Conf]
  6. V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi
    Routing architecture exploration for regular fabrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:204-207 [Conf]
  7. Vladimir Koval, Igor W. Farmaga, Andrzej J. Strojwas, Stephen W. Director
    MONSTR: A Complete Thermal Simulator of Electronic Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:570-575 [Conf]
  8. Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas
    Impact of interconnect variations on the clock skew of a gigahertz microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:168-171 [Conf]
  9. Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
    ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:469-472 [Conf]
  10. Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
    Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:201-206 [Conf]
  11. N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang
    When bad things happen to good chips (panel session). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:736-737 [Conf]
  12. Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, V. Rovner, K. Y. Tong
    Exploring regular fabrics to optimize the performance-cost trade-off. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:782-787 [Conf]
  13. Andrzej J. Strojwas
    Design for Manufacturability and Yield. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:454-459 [Conf]
  14. Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper
    Yield of VLSI circuits: myths vs. reality (panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:234-235 [Conf]
  15. D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas
    A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:579-584 [Conf]
  16. Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma
    Correlation-aware statistical timing analysis with non-gaussian delay distributions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:77-82 [Conf]
  17. Andrzej J. Strojwas
    CMU-CAM system. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:319-325 [Conf]
  18. Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
    Congestion-Aware Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:664-671 [Conf]
  19. Kimon W. Michaels, Andrzej J. Strojwas
    Variable Accuracy Device Modeling for Event-Driven Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:557-561 [Conf]
  20. Mukund Sivaraman, Andrzej J. Strojwas
    Towards Incorporating Device Parameter Variations in Timing Analysis. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:338-342 [Conf]
  21. Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
    Bounding the efforts on congestion optimization for physical synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:7-10 [Conf]
  22. Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas
    Projection-based performance modeling for inter/intra-die variations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:721-727 [Conf]
  23. Kimon W. Michaels, Andrzej J. Strojwas
    A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:254-257 [Conf]
  24. Mukund Sivaraman, Andrzej J. Strojwas
    Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:494-501 [Conf]
  25. Mukund Sivaraman, Andrzej J. Strojwas
    Timing analysis based on primitive path delay fault identification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:182-189 [Conf]
  26. Andrzej J. Strojwas
    Design-Manufacturing Interface for 0.13 Micron and Below. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:575- [Conf]
  27. Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark
    Statistical critical path analysis considering correlations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:699-704 [Conf]
  28. Jin-Qin Lu, Kimihiro Ogawa, Takehiko Adachi, Andrzej J. Strojwas
    Stochastic Interpolation Model Scheme for Statistical Circuit Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:125-128 [Conf]
  29. Andrzej J. Strojwas, Michele Quarantelli, J. Borel, Carlo Guardiani, G. Nicollini, G. Crisenza, Bruno Franzini, J. Wiart
    Manufacturability of low power CMOS technology solutions. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:225-232 [Conf]
  30. Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
    A pattern matching algorithm for verification and analysis of very large IC layouts. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:129-134 [Conf]
  31. Andrzej J. Strojwas
    Tutorial on DFM for physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:103- [Conf]
  32. Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
    Understanding and addressing the impact of wiring congestion during technology mapping. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:131-136 [Conf]
  33. Carlo Guardiani, Andrzej J. Strojwas
    Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead? [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:447-0 [Conf]
  34. Jacques Benkoski, Andrzej J. Strojwas
    Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:153-160 [Conf]
  35. Mukund Sivaraman, Andrzej J. Strojwas
    Test Vector Generation for Parametric Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:132-138 [Conf]
  36. Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark
    Statistical Critical Path Analysis Considering Correlations. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:364-373 [Conf]
  37. Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, Purnendu K. Mozumder, Andrzej J. Strojwas
    A New Methodology for Concurrent Technology Development and Cell Library Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:18-25 [Conf]
  38. Mukund Sivaraman, Andrzej J. Strojwas
    Diagnosis of parametric path delay faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:412-417 [Conf]
  39. Mukund Sivaraman, Andrzej J. Strojwas
    Primitive Path Delay Fault Identification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:95-100 [Conf]
  40. Mukund Sivaraman, Andrzej J. Strojwas
    A diagnosability metric for parametric path delay faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:316-323 [Conf]
  41. Juan Antonio Carballo, Yervant Zorian, Raul Camposano, Andrzej J. Strojwas, John Kibarian, Dennis Wassung, Alex Alexanian, Steve Wigley, Neil Kelly
    Guest Editors' Introduction: DFM Drives Changes in Design Flow. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:3, pp:200-205 [Journal]
  42. Jacques Benkoski, Andrzej J. Strojwas
    A New Approach to Hierarchical and Statistical Timing Simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1039-1052 [Journal]
  43. Ihao Chen, Andrzej J. Strojwas
    A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:592-600 [Journal]
  44. Ihao Chen, Andrzej J. Strojwas
    Realistic Yield Simulation for VLSIC Structural Failures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:965-980 [Journal]
  45. Robert W. Dutton, Andrzej J. Strojwas
    Perspectives on technology and technology-driven CAD. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1544-1560 [Journal]
  46. Shigetaka Kumashiro, Ronald A. Rohrer, Andrzej J. Strojwas
    Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:988-996 [Journal]
  47. Wojciech Maly, Andrzej J. Strojwas
    Statistical Simulation of the IC Manufacturing Process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1982, v:1, n:3, pp:120-131 [Journal]
  48. Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director
    VLSI Yield Prediction and Estimation: A Unified Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:114-130 [Journal]
  49. Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
    FABRICS II: A Statistically Based IC Fabrication Process Simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:1, pp:40-46 [Journal]
  50. Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
    A Methodology for Worst-Case Analysis of Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:104-113 [Journal]
  51. Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
    An algorithm for determining repetitive patterns in very large IC layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:494-501 [Journal]
  52. Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
    Global and local congestion optimization in technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:498-505 [Journal]
  53. Rahul Razdan, Andrzej J. Strojwas
    A Statistical Design Rule Developer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:508-520 [Journal]
  54. Mukund Sivaraman, Andrzej J. Strojwas
    Primitive path delay faults: identification and their use in timinganalysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1347-1362 [Journal]
  55. Mukund Sivaraman, Andrzej J. Strojwas
    Path delay fault diagnosis and coverage-a metric and an estimationtechnique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:440-457 [Journal]
  56. Andrzej J. Strojwas, Stephen W. Director
    A Pattern Recognition Based Method for IC Failure Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:76-92 [Journal]
  57. Andrzej J. Strojwas, Stephen W. Director
    An efficient algorithm for parametric fault simulation of monolithic IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1049-1058 [Journal]
  58. Xiaowei Tian, Andrzej J. Strojwas
    Numerical integral method for diffusion modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:9, pp:1110-1124 [Journal]
  59. D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas
    The CDB/HCDB semiconductor wafer representation server. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:283-295 [Journal]
  60. Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki
    DFM/DFY: should you trust the surgeon or the family doctor? [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:439-442 [Conf]

  61. Creating an affordable 22nm node using design-lithography co-optimization. [Citation Graph (, )][DBLP]


  62. Who solves the variability problem? [Citation Graph (, )][DBLP]


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