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Kuo-Liang Cheng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    Design and test of a scalable security processor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:372-375 [Conf]
  2. Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
    Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:91-96 [Conf]
  3. Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
    Test Scheduling and Test Access Architecture Optimization for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:411-0 [Conf]
  4. Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
    Test Scheduling of BISTed Memory Cores for SOC. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:356-0 [Conf]
  5. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
    Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:301-306 [Conf]
  6. Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
    Flash Memory Built-In Self-Test Using March-Like Algorithm. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:137-141 [Conf]
  7. Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
    FAME: A Fault-Pattern Based Memory Failure Analysis Framework. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:595-598 [Conf]
  8. Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
    Error Catch and Analysis for Semiconductor Memories Using March Tests. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:468-471 [Conf]
  9. Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee
    An SOC Test Integration Platform and Its Industrial Realization. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1213-1222 [Conf]
  10. Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    March-based RAM diagnosis algorithms for stuck-at and coupling faults. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:758-767 [Conf]
  11. Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
    Fault Pattern Oriented Defect Diagnosis for Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:29-38 [Conf]
  12. Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
    Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:225-230 [Conf]
  13. Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
    RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:281-288 [Conf]
  14. Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    Test and Diagnosis of Word-Oriented Multiport Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:248-253 [Conf]
  15. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
    Simulation-Based Test Algorithm Generation for Random Access Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:291-296 [Conf]
  16. Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu
    Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1328-1336 [Journal]
  17. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
    Fault simulation and test algorithm generation for random accessmemories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:480-490 [Journal]
  18. Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
    STEAC: A Platform for Automatic SOC Test Integration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:541-545 [Journal]

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