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Peter Suaris: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter Suaris, Dongsheng Wang, Nan-Chi Chou
    A practical cut-based physical retiming algorithm for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1027-1030 [Conf]
  2. Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska
    Fast post-placement rewiring using easily detectable functional symmetries. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:286-289 [Conf]
  3. Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu
    An algebraic multigrid solver for analytical placement with layout based clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:794-799 [Conf]
  4. Ajay J. Daga, Peter Suaris
    Interface Timing Verification Drives System Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:240-245 [Conf]
  5. Lalgudi N. Kannan, Peter Suaris, Hong-Gee Fang
    A Methodology and Algorithms for Post-Placement Delay Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:327-332 [Conf]
  6. Yuzheng Ding, Peter Suaris, Nan-Chi Chou
    The effect of post-layout pin permutation on timing. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:41-50 [Conf]
  7. Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris
    Fast adders in modern FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:250- [Conf]
  8. Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou
    Incremental physical resynthesis for timing optimization. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:99-108 [Conf]
  9. Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou
    A physical retiming algorithm for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:247- [Conf]
  10. Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge
    Total power-optimal pipelining and parallel processing under process variations in nanometer technology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:535-540 [Conf]
  11. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris
    Improving the efficiency of static timing analysis with false paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:527-531 [Conf]
  12. Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris
    Unified quadratic programming approach for mixed mode placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:193-199 [Conf]
  13. Dongsheng Wang, Peter Suaris, Nan-Chi Chou
    A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:511-519 [Conf]

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