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Publications of Author

1. Reiji Suda, Yoshio Oyanagi
   The Ensparsed LU Decomposition Method for Large Scale Circuit Transient Analysis. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1998, pp:507-512 [Conf]
   
2. Reiji Suda, Yoshio Oyanagi
   Implementation of Sparta, a Highly Parallel Circuit Simulator by the Preconditioned Jacobi Method, on a Distributed Memory Machine. [Citation Graph (0, 0)][DBLP]
   International Conference on Supercomputing, 1995, pp:209-217 [Conf]
   
3. Tamito Kajiyama, Akira Nukada, Hidehiko Hasegawa, Reiji Suda, Akira Nishida
   SILC: A Flexible and Environment-Independent Interface for Matrix Computation Libraries. [Citation Graph (0, 0)][DBLP]
   PPAM, 2005, pp:928-935 [Conf]
   
4. Reiji Suda, Masayasu Takami
   A fast spherical harmonics transform algorithm. [Citation Graph (0, 0)][DBLP]
   Math. Comput., 2002, v:71, n:238, pp:703-715 [Journal]
   
5. Reiji Suda, Akira Nishida, Yoshio Oyanagi
   A high performance parallelization scheme for the Hessenberg double shift QR algorithm. [Citation Graph (0, 0)][DBLP]
   Parallel Computing, 1999, v:25, n:6, pp:729-744 [Journal]
   
6. Reiji Suda, Ryotaro Kamikawai, Yasuo Wada, Willy Hioe, Mutsumi Hosoya, Eiichi Goto
   QFP wiring problem-introduction and analytical considerations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:48-56 [Journal]
   
7. Akira Nukada, Daisuke Takahashi, Reiji Suda, Akira Nishida
   High Performance FFT on SGI Altix 3700. [Citation Graph (0, 0)][DBLP]
   HPCC, 2007, pp:396-407 [Conf]
   
8. Tamito Kajiyama, Akira Nukada, Reiji Suda, Hidehiko Hasegawa, Akira Nishida
   Distributed SILC: An Easy-to-Use Interface for MPI-Based Parallel Matrix Computation Libraries. [Citation Graph (0, 0)][DBLP]
   PARA, 2006, pp:860-870 [Conf]
   
9. 
   Aspects of GPU for general purpose high performance computing. [Citation Graph (, )][DBLP]
   
   
10. 
    An optimized Dynamic Load Balancing method for parallel 3-D mesh refinement for finite element electromagnetics with Tetrahedra. [Citation Graph (, )][DBLP]
    
    
11. 
    Divisible load scheduling with improved asymptotic optimality. [Citation Graph (, )][DBLP]
    
    
12. 
    Accurate Measurements and Precise Modeling of Power Dissipation of CUDA Kernels toward Power Optimized High Performance CPU-GPU Computing. [Citation Graph (, )][DBLP]
    
    
13. 
    Cloth Simulation in the SILC Matrix Computation Framework: A Case Study. [Citation Graph (, )][DBLP]
    
    
14. 
    Modeling and Optimizing the Power Performance of Large Matrices Multiplication on Multi-core and GPU Platform with CUDA. [Citation Graph (, )][DBLP]
    
    
15. 
    Parallel Minimax Tree Searching on GPU. [Citation Graph (, )][DBLP]
    
    
16. 
    Power Efficient Large Matrices Multiplication by Load Scheduling on Multi-core and GPU Platform with CUDA. [Citation Graph (, )][DBLP]
    
    
17. 
    Modeling and Estimation for the Power Consumption of Matrix Computation on Multi-core Platform. [Citation Graph (, )][DBLP]