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Publications of Author

1. Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda
   A perturbation-aware noise convergence methodology for high frequency microprocessors. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:717-722 [Conf]
   
2. Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang
   Realizable parasitic reduction for distributed interconnects using matrix pencil technique. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:780-785 [Conf]
   
3. Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar
   Net weighting to reduce repeater counts during placement. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:503-508 [Conf]
   
4. Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
   Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. [Citation Graph (0, 0)][DBLP]
   DAC, 2001, pp:732-737 [Conf]
   
5. Prashant Saxena, Bill Halpin
   Modeling repeaters explicitly within analytical placement. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:699-704 [Conf]
   
6. Prashant Saxena, C. L. Liu
   Crosstalk Minimization Using Wire Perturbations. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:100-103 [Conf]
   
7. Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu
   A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   Euro-Par, Vol. I, 1996, pp:828-831 [Conf]
   
8. Prashant Saxena, C. L. Liu
   A performance-driven layer assignment algorithm for multiple interconnect trees. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:124-127 [Conf]
   
9. B. Chappell, X. Wang, P. Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain
   A System-Level Solution to Domino Synthesis with 2 GHz Application. [Citation Graph (0, 0)][DBLP]
   ICCD, 2002, pp:164-0 [Conf]
   
10. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
    A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6230-6233 [Conf]
    
11. Desmond Kirkpatrick, Pete Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester
    The great interconnect buffering debate: are you a chicken or an ostrich? [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:61- [Conf]
    
12. Prashant Saxena, Satyanarayan Gupta
    Shield count minimization in congested regions. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:78-83 [Conf]
    
13. Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
    The scaling challenge: can correct-by-construction design help? [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:51-58 [Conf]
    
14. Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
    A predictive distributed congestion metric and its application to technology mapping. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:210-217 [Conf]
    
15. Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar
    An efficient technology mapping algorithm targeting routing congestion under delay constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:137-144 [Conf]
    
16. Prashant Saxena
    The scaling of interconnect buffer needs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:109-112 [Conf]
    
17. Prashant Saxena, Peichen Pan, C. L. Liu
    The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:402-407 [Conf]
    
18. Aviezri S. Fraenkel, Edward M. Reingold, Prashant Saxena
    Efficient Management of Dynamic Tables. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1994, v:50, n:1, pp:25-30 [Journal]
    
19. Prashant Saxena
    On controlling perturbation due to repeaters during quadratic placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1733-1743 [Journal]
    
20. Prashant Saxena, Satyanarayan Gupta
    On integrating power and signal routing for shield count minimization in congested regions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:437-445 [Journal]
    
21. Prashant Saxena, C. L. Liu
    A postprocessing algorithm for crosstalk-driven wire perturbation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:6, pp:691-702 [Journal]
    
22. Prashant Saxena, C. L. Liu
    Optimization of the maximum delay of global interconnects duringlayer assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:503-515 [Journal]
    
23. Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
    Repeater scaling and its impact on CAD. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:451-463 [Journal]
    
24. Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar
    Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:625-636 [Journal]
    
25. Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
    A predictive distributed congestion metric with application to technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:696-710 [Journal]
    
26. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
    Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:879-887 [Journal]
    
27. 
    On improving optimization effectiveness in interconnect-driven physical synthesis. [Citation Graph (, )][DBLP]