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Dimitrios Soudris: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dimitrios Soudris, Spiridon Nikolaidis, S. Siskos, Konstantinos Tatas, K. Siozios, G. Koutroumpezis, Nikolaos Vassiliadis, V. Kalenteridis, H. Pournara, I. Pappas, Adonios Thanailakis
    AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:3-4 [Conf]
  2. Dimitrios Soudris, Michael K. Birbas, Constantinos E. Goutis
    Direct mapping of nested loops on piecewise regular processor arrays. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:145-150 [Conf]
  3. David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris
    Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:532-537 [Conf]
  4. Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:740-745 [Conf]
  5. Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:946-947 [Conf]
  6. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:247-252 [Conf]
  7. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:247-252 [Conf]
  8. Nikolaos D. Liveris, Nikolaos D. Zervas, Dimitrios Soudris, Constantinos E. Goutis
    A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:977-983 [Conf]
  9. Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias
    Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:874-875 [Conf]
  10. Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris
    Energy-efficient dynamic memory allocators at the middleware level of embedded systems. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2006, pp:215-222 [Conf]
  11. David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris
    Reducing memory accesses with a system-level design methodology in customized dynamic memory management. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2004, pp:93-98 [Conf]
  12. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:275-276 [Conf]
  13. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:252- [Conf]
  14. K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis
    A novel methodology for designing high-performance and low-energy FPGA routing architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:224- [Conf]
  15. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:868-873 [Conf]
  16. G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis
    Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1027-1036 [Conf]
  17. K. Siozios, G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
    A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1116-1118 [Conf]
  18. K. Siozios, Dimitrios Soudris, Adonios Thanailakis
    A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:707-708 [Conf]
  19. Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis
    Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1032-1035 [Conf]
  20. I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis
    Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:83-88 [Conf]
  21. Antonios Atsalakis, Nikos Papamarkos, Dimitrios Soudris, Nikolas Kroupis
    A window-based color quantization technique and its embedded implementation. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 2002, pp:365-368 [Conf]
  22. Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis
    Power, performance and area exploration of block matching algorithms mapped on programmable processors. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2001, pp:728-731 [Conf]
  23. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  24. K. Siozios, G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
    DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  25. Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
    Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  26. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A methodology for partitioning DSP applications in hybrid reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1206-1209 [Conf]
  27. Vassilis Paliouras, Dimitrios Soudris, Thanos Stouraitis
    Methodology for the Design of Signed-digit DSP Processors. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1833-1836 [Conf]
  28. Dimitrios Soudris, P. D. Georgakopoulos, Constantinos E. Goutis
    A Systematic Methodology for Designing Multilevel Systolic Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1738-1741 [Conf]
  29. Dimitrios Soudris, Marios Kesoulis, C. Koukourlis, Adonios Thanailakis, Spyros Blionas
    Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:73-76 [Conf]
  30. Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis
    A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:129-132 [Conf]
  31. Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis
    A reusable IP FFT core for DSP applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:621-624 [Conf]
  32. Nikolaos D. Zervas, I. Tagopoulos, Vassilis Spiliotopoulos, Giorgos P. Anagnostopoulos, Dimitrios Soudris, Constantinos E. Goutis
    Performance comparison of DWT scheduling alternatives on programmable platforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:761-764 [Conf]
  33. Christos Drosos, Chrissavgi Dre, Spyros Blionas, Dimitrios Soudris
    On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:334-337 [Conf]
  34. I. Thoidis, Dimitrios Soudris, J. M. Fernandez, Adonios Thanailakis
    The circuit design of multiple-valued logic voltage-mode adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:162-165 [Conf]
  35. M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, G. A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis
    The VLSI implementation of a baseband receiver for DECT-based portable applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:198-201 [Conf]
  36. George Theodoridis, S. Theoharis, Dimitrios Soudris, Thanos Stouraitis, Constantinos E. Goutis
    An efficient probabilistic method for logic circuits using real delay gate model. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:286-289 [Conf]
  37. Athanasios Kakarountas, K. Papadomanolakis, Spiridon Nikolaidis, Dimitrios Soudris, Constantinos E. Goutis
    Confronting violations of the TSCG(T) in low-power design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:313-316 [Conf]
  38. Konstantinos Tatas, Antonios Argyriou, Minas Dasygenis, Dimitrios Soudris, Nikolaos D. Zervas
    Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:456-461 [Conf]
  39. Lazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris
    Application - specific NoC platform design based on System Level Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:311-316 [Conf]
  40. Kostas Siozios, Dimitrios Soudris
    A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:55-60 [Conf]
  41. David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris
    Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:510-520 [Conf]
  42. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:652-661 [Conf]
  43. Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    Improving the Memory Bandwidth Utilization Using Loop Transformations. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:117-126 [Conf]
  44. Kostas Masselos, Spyros Blionas, Jean-Yves Mignolet, A. Foster, Dimitrios Soudris, Spiridon Nikolaidis
    Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:613-622 [Conf]
  45. Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas
    Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:430-439 [Conf]
  46. Nikolaos D. Zervas, G. Pagkless, Minas Dasygenis, Dimitrios Soudris
    Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:323-331 [Conf]
  47. Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:47-55 [Conf]
  48. Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis
    Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:403-414 [Conf]
  49. Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis
    Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:243-254 [Conf]
  50. Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:540-549 [Conf]
  51. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
    A Novel Data-Path for Accelerating DSP Kernels. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:363-372 [Conf]
  52. Marios Kesoulis, Dimitrios Soudris, C. Koukourlis, Adonios Thanailakis
    Designing Low Power Direct Digital Frequency Synthesizers. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:105-110 [Conf]
  53. Nikolas Kroupis, Minas Dasygenis, Dimitrios Soudris, Antonios Thanailakis
    A Modified Spiral Search Algorithm and its Embedded Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    IEC (Prague), 2005, pp:375-378 [Conf]
  54. Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis
    Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. [Citation Graph (0, 0)][DBLP]
    WWIC, 2005, pp:354-364 [Conf]
  55. Stylianos Mamagkakis, Alexandros Mpartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Antonios Thanailakis
    Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. [Citation Graph (0, 0)][DBLP]
    WWIC, 2004, pp:26-37 [Conf]
  56. Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2006, v:29, n:13-14, pp:2612-2620 [Journal]
  57. David Atienza, Stylianos Mamagkakis, Francesco Poletti, Jose Manuel Mendias, Francky Catthoor, Luca Benini, Dimitrios Soudris
    Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:2, pp:113-130 [Journal]
  58. Konstantinos Tatas, G. Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis
    Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:74-93 [Journal]
  59. Laurence Tianruo Yang, José G. Delgado-Frias, Yiming Li, Mohammed Niamat, Dimitrios Soudris, Srinivasa Vemuru
    Preface. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:61- [Journal]
  60. Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis
    A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:2, pp:281-296 [Journal]
  61. S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis
    A fast and accurate delay dependent method for switching estimation of large combinational circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:4-5, pp:113-124 [Journal]
  62. Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis
    Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 2003, v:9, n:6, pp:371-386 [Journal]
  63. David Atienza, Jose Manuel Mendias, Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor
    Systematic dynamic memory management design methodology for reduced memory footprint. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:465-489 [Journal]
  64. Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis
    A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:279-291 [Journal]
  65. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2007, v:31, n:1, pp:1-14 [Journal]
  66. Nikolaos D. Zervas, George Theodoridis, Dimitrios Soudris
    Behavioral-level event-driven power management for DECT digital receivers. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:2, pp:163-172 [Journal]
  67. Christos Drosos, Chrissavgi Dre, Dimitris Metafas, Dimitrios Soudris, Spyros Blionas
    The low power analogue and digital baseband processing parts of a novel multimode DECT/GSM/DCS1800 terminal. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2004, v:35, n:7, pp:609-620 [Journal]
  68. Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor
    Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1036-1041 [Conf]
  69. Kostas Siozios, Dimitrios Soudris
    Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  70. Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis
    A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  71. Alexandros Bartzas, M. Peón, Stylianos Mamagkakis, David Atienza, F. Catthoort, Dimitrios Soudris, M. Mendias
    Systematic design flow for dynamic data management in visual texture decoder of MPEG-4. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  72. Miguel Peon-Quiros, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris
    Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:373-383 [Conf]
  73. Nikolas Kroupis, Dimitrios Soudris
    Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:505-515 [Conf]
  74. Lazaros Papadopoulos, Dimitrios Soudris
    System-Level Application-Specific NoC Design for Network and Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:1-9 [Conf]
  75. Lazaros Papadopoulos, Christos Baloukas, Nikolaos Zompakis, Dimitrios Soudris
    Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:58-65 [Conf]
  76. Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis
    Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:204-209 [Conf]
  77. Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis
    Designing Heterogeneous FPGAs with Multiple SBs. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:91-96 [Conf]
  78. Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  79. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  80. Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:7, pp:417-436 [Journal]
  81. Athanasios Kakarountas, Nikolaos D. Zervas, George Theodoridis, Haralambos Michail, Dimitrios Soudris
    Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:356-364 [Journal]
  82. Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis
    Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:1-2, pp:153-171 [Journal]

  83. Data Structure Exploration of Dynamic Applications. [Citation Graph (, )][DBLP]


  84. Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information. [Citation Graph (, )][DBLP]


  85. A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms. [Citation Graph (, )][DBLP]


  86. A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs. [Citation Graph (, )][DBLP]


  87. Construction of dual mode components for reconfiguration aware high-level synthesis. [Citation Graph (, )][DBLP]


  88. Compilation Technique for Loop Overhead Minimization. [Citation Graph (, )][DBLP]


  89. Component Based Library Implementation of Abstract Data Types for Resource Management Customization of Embedded Systems. [Citation Graph (, )][DBLP]


  90. An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems. [Citation Graph (, )][DBLP]


  91. Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support. [Citation Graph (, )][DBLP]


  92. A modified spiral search motion estimation algorithm and its embedded system implementation. [Citation Graph (, )][DBLP]


  93. Dynamic Data Type Optimization and Memory Assignment Methodologies. [Citation Graph (, )][DBLP]


  94. Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip. [Citation Graph (, )][DBLP]


  95. An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs. [Citation Graph (, )][DBLP]


  96. Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms. [Citation Graph (, )][DBLP]


  97. Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation. [Citation Graph (, )][DBLP]


  98. A software-supported methodology for designing high-performance 3D FPGA architectures. [Citation Graph (, )][DBLP]


  99. Implementing cellular automata modeled applications on network-on-chip platforms. [Citation Graph (, )][DBLP]


  100. A Framework for Enabling Fault Tolerance in Reconfigurable Architectures. [Citation Graph (, )][DBLP]


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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002