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Konstantinos Tatas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dimitrios Soudris, Spiridon Nikolaidis, S. Siskos, Konstantinos Tatas, K. Siozios, G. Koutroumpezis, Nikolaos Vassiliadis, V. Kalenteridis, H. Pournara, I. Pappas, Adonios Thanailakis
    AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:3-4 [Conf]
  2. K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis
    A novel methodology for designing high-performance and low-energy FPGA routing architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:224- [Conf]
  3. G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis
    Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1027-1036 [Conf]
  4. K. Siozios, G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
    A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1116-1118 [Conf]
  5. K. Siozios, Konstantinos Tatas, G. Koutroumpezis, D. J. Soudris, Adonios Thanailakis
    An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:658-661 [Conf]
  6. Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis
    Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1032-1035 [Conf]
  7. Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis
    Power, performance and area exploration of block matching algorithms mapped on programmable processors. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2001, pp:728-731 [Conf]
  8. V. Kalenteridis, H. Pournara, K. Siozios, Konstantinos Tatas, G. Koutroumpezis, I. Pappas, Spiridon Nikolaidis, S. Siskos, D. J. Soudris, Adonios Thanailakis
    An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  9. K. Siozios, G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
    DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  10. Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
    Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  11. Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis
    A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:129-132 [Conf]
  12. Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis
    A reusable IP FFT core for DSP applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:621-624 [Conf]
  13. Konstantinos Tatas, Antonios Argyriou, Minas Dasygenis, Dimitrios Soudris, Nikolaos D. Zervas
    Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:456-461 [Conf]
  14. Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas
    Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:430-439 [Conf]
  15. Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, S. Siskos, Adonios Thanailakis
    FPGA Architecture Design and Toolset for Logic Implementation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:607-616 [Conf]
  16. Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis
    Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:243-254 [Conf]
  17. Konstantinos Tatas, G. Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis
    Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:74-93 [Journal]
  18. Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis
    A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:2, pp:281-296 [Journal]
  19. Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis
    Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 2003, v:9, n:6, pp:371-386 [Journal]
  20. V. Kalenteridis, H. Pournara, K. Siozios, Konstantinos Tatas, Nikolaos Vassiliadis, I. Pappas, G. Koutroumpezis, Spiridon Nikolaidis, S. Siskos, D. J. Soudris
    A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:6, pp:247-259 [Journal]
  21. Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis
    Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:1-2, pp:153-171 [Journal]

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