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Adonios Thanailakis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dimitrios Soudris, Spiridon Nikolaidis, S. Siskos, Konstantinos Tatas, K. Siozios, G. Koutroumpezis, Nikolaos Vassiliadis, V. Kalenteridis, H. Pournara, I. Pappas, Adonios Thanailakis
    AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:3-4 [Conf]
  2. G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis
    Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1027-1036 [Conf]
  3. K. Siozios, G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
    A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1116-1118 [Conf]
  4. K. Siozios, Dimitrios Soudris, Adonios Thanailakis
    A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:707-708 [Conf]
  5. K. Siozios, Konstantinos Tatas, G. Koutroumpezis, D. J. Soudris, Adonios Thanailakis
    An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:658-661 [Conf]
  6. Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis
    Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1032-1035 [Conf]
  7. I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis
    Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:83-88 [Conf]
  8. V. Kalenteridis, H. Pournara, K. Siozios, Konstantinos Tatas, G. Koutroumpezis, I. Pappas, Spiridon Nikolaidis, S. Siskos, D. J. Soudris, Adonios Thanailakis
    An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  9. K. Siozios, G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
    DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  10. Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis
    Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  11. Dimitrios Soudris, Marios Kesoulis, C. Koukourlis, Adonios Thanailakis, Spyros Blionas
    Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:73-76 [Conf]
  12. Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis
    A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:129-132 [Conf]
  13. D. J. Soudris, M. M. Dasigenis, S. K. Vasilopoulou, Adonios Thanailakis
    A CAD tool for architecture level exploration and automatic generation of RNS converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:730-733 [Conf]
  14. I. Thoidis, Dimitrios Soudris, J. M. Fernandez, Adonios Thanailakis
    The circuit design of multiple-valued logic voltage-mode adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:162-165 [Conf]
  15. M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, G. A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis
    The VLSI implementation of a baseband receiver for DECT-based portable applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:198-201 [Conf]
  16. Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas
    Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:430-439 [Conf]
  17. Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, S. Siskos, Adonios Thanailakis
    FPGA Architecture Design and Toolset for Logic Implementation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:607-616 [Conf]
  18. Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis
    Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:243-254 [Conf]
  19. Marios Kesoulis, Dimitrios Soudris, C. Koukourlis, Adonios Thanailakis
    Designing Low Power Direct Digital Frequency Synthesizers. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:105-110 [Conf]
  20. Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis
    A cellular automaton methodology for the simulation of integrated circuit fabrication processes. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2002, v:18, n:5, pp:639-657 [Journal]
  21. Konstantinos Tatas, G. Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis
    Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:74-93 [Journal]
  22. Panagiotis Tzionas, Adonios Thanailakis, Philippos Tsalides
    An efficient algorithm for the largest empty figure problem based on a 2D cellular automaton architecture. [Citation Graph (0, 0)][DBLP]
    Image Vision Comput., 1997, v:15, n:1, pp:35-45 [Journal]
  23. Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis
    A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:2, pp:281-296 [Journal]
  24. Howard C. Card, Adonios Thanailakis, Werner Pries, Robert D. McLeod
    Analysis of Bounded Linear Cellular Automata Based on a Method of Image Charges. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 1986, v:33, n:3, pp:473-480 [Journal]
  25. S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis
    A fast and accurate delay dependent method for switching estimation of large combinational circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:4-5, pp:113-124 [Journal]
  26. E. D. Adamides, Philippos Tsalides, Adonios Thanailakis
    Synchronization of D. Parkinsonasynchronous concurrent processes using cellular automata. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1989, v:11, n:2, pp:163-169 [Journal]
  27. E. D. Adamides, Philippos Tsalides, Adonios Thanailakis
    Hierarchical Cellular Automata structures. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1992, v:18, n:5, pp:517-524 [Journal]
  28. Ioannis Karafyllidis, Ioannis Andreadis, Panagiotis Tzionas, Philippos Tsalides, Adonios Thanailakis
    A cellular automaton for the determination of the mean velocity of moving objects and its VLSI implementation. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1996, v:29, n:4, pp:689-699 [Journal]
  29. Ioannis Karafyllidis, A. Ioannidis, Adonios Thanailakis, Phillipos Tsalides
    Geometrical Shape Recognition Using a Cellular Automaton Architecture and its VLSI Implementation. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1997, v:3, n:4, pp:243-254 [Journal]
  30. Panagiotis Tzionas, Phillipos Tsalides, Adonios Thanailakis
    A Parallel Skeletonization Algorithm Based on Two-Dimensional Cellular Automata and its VLSI Implementation. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1995, v:1, n:2, pp:105-117 [Journal]
  31. Werner Pries, Adonios Thanailakis, Howard C. Card
    Group Properties of Cellular Automata and VLSI Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:12, pp:1013-1024 [Journal]
  32. Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis
    A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:279-291 [Journal]
  33. Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis
    A CAD system for the construction and VLSI implementation of Cellular Automata algorithms using VHDL. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:8, pp:381-396 [Journal]
  34. Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis
    A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  35. A modified spiral search motion estimation algorithm and its embedded system implementation. [Citation Graph (, )][DBLP]


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