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H. C. Srinivasaiah: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. H. C. Srinivasaiah, Navakanta Bhat
    Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:225-232 [Conf]
  2. H. C. Srinivasaiah, Navakanta Bhat
    Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:225-0 [Conf]
  3. H. C. Srinivasaiah, Navakanta Bhat
    Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:285-290 [Conf]
  4. H. C. Srinivasaiah, Navakanta Bhat
    Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:742-747 [Journal]

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