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Navakanta Bhat: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. H. C. Srinivasaiah, Navakanta Bhat
    Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:225-232 [Conf]
  2. S. Jairam, C. Venkatesh, Navakanta Bhat, Shyam Singh, Rudra Pratap
    A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:642-645 [Conf]
  3. H. C. Srinivasaiah, Navakanta Bhat
    Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:225-0 [Conf]
  4. H. C. Srinivasaiah, Navakanta Bhat
    Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:285-290 [Conf]
  5. R. Srinivasan, Navakanta Bhat
    Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC's. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:105-109 [Conf]
  6. R. Srinivasan, Navakanta Bhat
    Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:392-396 [Conf]
  7. B. P. Harish, Navakanta Bhat, Mahesh B. Patil
    Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs. [Citation Graph (0, 0)][DBLP]
    ICCTA, 2007, pp:94-98 [Conf]
  8. Shashidhar Pati, C. Venkatesh, Navakanta Bhat, Rudra Pratap
    Voltage Controlled Oscillator Using Tunable Mems Resonator. [Citation Graph (0, 0)][DBLP]
    International Journal of Computational Engineering Science, 2003, v:4, n:3, pp:675-678 [Journal]
  9. C. Venkatesh, Shashidhar Pati, Navakanta Bhat
    Torsional Mems Varactor With Low Actuation Voltage. [Citation Graph (0, 0)][DBLP]
    International Journal of Computational Engineering Science, 2003, v:4, n:3, pp:555-558 [Journal]
  10. H. C. Srinivasaiah, Navakanta Bhat
    Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:742-747 [Journal]
  11. Balaji Jayaraman, Navakanta Bhat
    High Precision 16-bit Readout Gas Sensor Interface in 0.13µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3071-3074 [Conf]

  12. A low power, process invariant keeper for high speed dynamic logic circuits. [Citation Graph (, )][DBLP]


  13. Optimal power and noise allocation for analog and digital sections of a low power radio receiver. [Citation Graph (, )][DBLP]


  14. Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis. [Citation Graph (, )][DBLP]


  15. GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes. [Citation Graph (, )][DBLP]


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