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Krishnan Srinivasan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Krishnan Srinivasan, Karam S. Chatha
    SAGA: synthesis technique for guaranteed throughput NoC architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:489-494 [Conf]
  2. Krishnan Srinivasan, Karam S. Chatha
    Layout aware design of mesh based NoC architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:136-141 [Conf]
  3. Krishnan Srinivasan, Karam S. Chatha
    A low complexity heuristic for design of custom network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:130-135 [Conf]
  4. Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
    An automated technique for topology and route generation of application specific on-chip interconnection networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:231-237 [Conf]
  5. Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
    Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:422-429 [Conf]
  6. Krishnan Srinivasan, Karam S. Chatha
    A technique for low energy mapping and routing in network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:387-392 [Conf]
  7. Krishnan Srinivasan, Karam S. Chatha
    A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:352-357 [Conf]
  8. Krishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha
    A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:313-316 [Conf]
  9. Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha
    System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:39-45 [Conf]
  10. Krishnan Srinivasan, Karam S. Chatha
    An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:255-260 [Conf]
  11. Krishnan Srinivasan, Karam S. Chatha
    ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:623-628 [Conf]
  12. Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
    Linear-programming-based techniques for synthesis of network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:407-420 [Journal]
  13. Krishnan Srinivasan, Karam S. Chatha
    Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:326-354 [Journal]
  14. Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan
    ILP and heuristic techniques for system-level design on network processor architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]

  15. Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. [Citation Graph (, )][DBLP]


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