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Karam S. Chatha: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Krishnan Srinivasan, Karam S. Chatha
    SAGA: synthesis technique for guaranteed throughput NoC architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:489-494 [Conf]
  2. Lina Peng, Gisik Kwon, Yinpeng Chen, K. Selçuk Candan, Hari Sundaram, Karam S. Chatha, Maria Luisa Sapino
    Modular Design of Media Retrieval Workflows Using ARIA. [Citation Graph (0, 0)][DBLP]
    CIVR, 2006, pp:491-494 [Conf]
  3. Karam S. Chatha, Ranga Vemuri
    MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:42-47 [Conf]
  4. Karam S. Chatha, Ranga Vemuri
    RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:139-143 [Conf]
  5. Krishnan Srinivasan, Karam S. Chatha
    Layout aware design of mesh based NoC architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:136-141 [Conf]
  6. Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha
    A Power and Performance Model for Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1250-1255 [Conf]
  7. Krishnan Srinivasan, Karam S. Chatha
    A low complexity heuristic for design of custom network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:130-135 [Conf]
  8. Karam S. Chatha, Ranga Vemuri
    Hardware-Software Codesign for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:175-184 [Conf]
  9. Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha
    Quality-of-service and error control techniques for network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:45-50 [Conf]
  10. Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
    An automated technique for topology and route generation of application specific on-chip interconnection networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:231-237 [Conf]
  11. Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
    Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:422-429 [Conf]
  12. Krishnan Srinivasan, Karam S. Chatha
    A technique for low energy mapping and routing in network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:387-392 [Conf]
  13. Krishnan Srinivasan, Karam S. Chatha
    A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:352-357 [Conf]
  14. Karam S. Chatha, Ranga Vemuri
    A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:145-151 [Conf]
  15. Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha
    System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:110-116 [Conf]
  16. Krishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha
    A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:313-316 [Conf]
  17. Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha
    System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:39-45 [Conf]
  18. K. Selçuk Candan, Lina Peng, Kyung Dong Ryu, Karam S. Chatha, Christopher B. Mayer
    Efficient Stream Routing in Quality- and Resource-Adaptive Flow Architectures. [Citation Graph (0, 0)][DBLP]
    Multimedia Information Systems, 2004, pp:30-39 [Conf]
  19. Lina Peng, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram
    ARIA: an adaptive and programmable media-flow architecture for interactive arts. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2004, pp:532-535 [Conf]
  20. Lina Peng, Gisik Kwon, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram, Yinpeng Chen
    Media processing workflow design and execution with ARIA. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2005, pp:800-801 [Conf]
  21. Karam S. Chatha, Ranga Vemuri
    Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:218-224 [Conf]
  22. Karam S. Chatha, Ranga Vemuri
    An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:134-139 [Conf]
  23. Nagendran Rangan, Karam S. Chatha
    A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:564-569 [Conf]
  24. Krishnan Srinivasan, Karam S. Chatha
    An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:255-260 [Conf]
  25. Krishnan Srinivasan, Karam S. Chatha
    ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:623-628 [Conf]
  26. Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha
    Quality-of-service and error control techniques for mesh-based network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:353-382 [Journal]
  27. Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
    Linear-programming-based techniques for synthesis of network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:407-420 [Journal]
  28. Christopher Ostler, Karam S. Chatha
    Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:801-804 [Conf]
  29. Christopher Ostler, Karam S. Chatha
    An ILP formulation for system-level application mapping on network processor architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:99-104 [Conf]
  30. Krishnan Srinivasan, Karam S. Chatha
    Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:326-354 [Journal]
  31. Lina Peng, K. Selçuk Candan, Christopher B. Mayer, Karam S. Chatha, Kyung Dong Ryu
    Optimization of media processing workflows with adaptive operator behaviors. [Citation Graph (0, 0)][DBLP]
    Multimedia Tools Appl., 2007, v:33, n:3, pp:245-272 [Journal]
  32. Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan
    ILP and heuristic techniques for system-level design on network processor architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]
  33. Karam S. Chatha, Ranga Vemuri
    Hardware-software partitioning and pipelined scheduling of transformative applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:193-208 [Journal]

  34. Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. [Citation Graph (, )][DBLP]


  35. Approximation Algorithm for Process Mapping on Network Processor Architectures. [Citation Graph (, )][DBLP]


  36. Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures. [Citation Graph (, )][DBLP]


  37. Performance and resource optimization of NoC router architecture for master and slave IP cores. [Citation Graph (, )][DBLP]


  38. Smart driver for power reduction in next generation bistable electrophoretic display technology. [Citation Graph (, )][DBLP]


  39. Power reduction via macroblock prioritization for power aware H.264 video applications. [Citation Graph (, )][DBLP]


  40. Automated technique for design of NoC with minimal communication latency. [Citation Graph (, )][DBLP]


  41. A scalable parallel H.264 decoder on the cell broadband engine architecture. [Citation Graph (, )][DBLP]


  42. Throughput optimal task allocation under thermal constraints for multi-core processors. [Citation Graph (, )][DBLP]


  43. Thermal aware task sequencing on embedded processors. [Citation Graph (, )][DBLP]


  44. Performance optimal speed control of multi-core processors under thermal constraints. [Citation Graph (, )][DBLP]


  45. Compilation of stream programs for multicore processors that incorporate scratchpad memories. [Citation Graph (, )][DBLP]


  46. Approximation algorithm for the temperature-aware scheduling problem. [Citation Graph (, )][DBLP]


  47. System-level thermal aware design of applications with uncertain execution time. [Citation Graph (, )][DBLP]


  48. Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. [Citation Graph (, )][DBLP]


  49. Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules. [Citation Graph (, )][DBLP]


  50. Near optimal battery-aware energy management. [Citation Graph (, )][DBLP]


  51. Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance. [Citation Graph (, )][DBLP]


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