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Evangeline F. Y. Young :
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Chiu-Wing Sham , Evangeline F. Y. Young Congestion prediction in floorplanning. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:1107-1110 [Conf ] Evangeline F. Y. Young , M. L. Ho , Chris C. N. Chu A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2002, pp:661-670 [Conf ] Chiu-Wing Sham , Evangeline F. Y. Young , Chris C. N. Chu Optimal cell flipping in placement and floorplanning. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:1109-1114 [Conf ] Chris C. N. Chu , Evangeline F. Y. Young Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:1101- [Conf ] Steve T. W. Lai , Evangeline F. Y. Young , Chris C. N. Chu A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:10856-10861 [Conf ] Wai-Chiu Wong , Chiu-Wing Sham , Evangeline F. Y. Young Congestion Estimation with Buffer Planning in Floorplan Design. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:696-701 [Conf ] Royce L. S. Ching , Evangeline F. Y. Young Shuttle mask floorplanning with modified alpha-restricted grid. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:85-90 [Conf ] Jill H. Y. Law , Evangeline F. Y. Young , Royce L. S. Ching Block alignment in 3D floorplan using layered TCG. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:376-380 [Conf ] Eric S. H. Wong , Evangeline F. Y. Young , Wai-Kei Mak Clustering based acyclic multi-way partitioning. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2003, pp:203-206 [Conf ] Chris C. N. Chu , Evangeline F. Y. Young , Dennis K. Y. Tong , Sampath Dechu Retiming with Interconnect and Gate Delay. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:221-226 [Conf ] Yiu-Cheong Tam , Evangeline F. Y. Young , Chris C. N. Chu Analog placement with symmetry and other placement constraints. [Citation Graph (0, 0)][DBLP ] ICCAD, 2006, pp:349-354 [Conf ] Royce L. S. Ching , Evangeline F. Y. Young , Kevin C. K. Leung , Chris Chu Post-placement voltage island generation. [Citation Graph (0, 0)][DBLP ] ICCAD, 2006, pp:641-646 [Conf ] Jill H. Y. Law , Evangeline F. Y. Young Multi-bend bus driven floorplanning. [Citation Graph (0, 0)][DBLP ] ISPD, 2005, pp:113-120 [Conf ] Chiu-Wing Sham , Evangeline F. Y. Young Routability driven floorplanner with buffer block planning. [Citation Graph (0, 0)][DBLP ] ISPD, 2002, pp:50-55 [Conf ] Wai-Kei Mak , Evangeline F. Y. Young Temporal logic replication for dynamically reconfigurable FPGA partitioning. [Citation Graph (0, 0)][DBLP ] ISPD, 2002, pp:190-195 [Conf ] Dennis K. Y. Tong , Evangeline F. Y. Young Performance-driven register insertion in placement. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:53-60 [Conf ] Evangeline F. Y. Young , Chris C. N. Chu , Zion Cien Shen Twin binary sequences: a non-redundant representation for general non-slicing floorplan. [Citation Graph (0, 0)][DBLP ] ISPD, 2002, pp:196-201 [Conf ] Chiu-Wing Sham , Evangeline F. Y. Young Congestion prediction in early stages. [Citation Graph (0, 0)][DBLP ] SLIP, 2005, pp:91-98 [Conf ] Evangeline F. Y. Young , Chris C. N. Chu , M. L. Ho A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2002, pp:661-0 [Conf ] Chris C. N. Chu , Evangeline F. Y. Young Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:71-79 [Journal ] Wai-Kei Mak , Evangeline F. Y. Young Temporal logic replication for dynamically reconfigurable FPGA partitioning. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:952-959 [Journal ] Chiu-Wing Sham , Evangeline F. Y. Young Routability-driven floorplanner with buffer block planning. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:470-480 [Journal ] Evangeline F. Y. Young , Chris C. N. Chu , W. S. Luk , Y. C. Wong Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:687-692 [Journal ] Evangeline F. Y. Young , Chris C. N. Chu , Zion Cien Shen Twin binary sequences: a nonredundant representation for general nonslicing floorplan. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:457-469 [Journal ] Evangeline F. Y. Young , Martin D. F. Wong , Hannah Honghua Yang Slicing floorplans with range constraint. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:272-278 [Journal ] Evangeline F. Y. Young , Martin D. F. Wong , Hannah Honghua Yang On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:800-807 [Journal ] Evangeline F. Y. Young , Martin D. F. Wong , Hannah Honghua Yang Slicing floorplans with boundary constraints. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1385-1389 [Journal ] Wing Seung Yuen , Evangeline F. Y. Young Slicing floorplan with clustering constraint. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:652-658 [Journal ] Evangeline F. Y. Young , Chris C. N. Chu , M. L. Ho Placement constraints in floorplan design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:735-745 [Journal ] Chiu-Wing Sham , Evangeline F. Y. Young Area reduction by deadspace utilization on interconnect optimized floorplan. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal ] Analog placement with common centroid and 1-D symmetry constraints. [Citation Graph (, )][DBLP ] TCG-based multi-bend bus driven floorplanning. [Citation Graph (, )][DBLP ] Analog placement with common centroid constraints. [Citation Graph (, )][DBLP ] Voltage island-driven floorplanning. [Citation Graph (, )][DBLP ] Network flow-based power optimization under timing constraints in MSV-driven floorplanning. [Citation Graph (, )][DBLP ] Obstacle-avoiding rectilinear Steiner tree construction. [Citation Graph (, )][DBLP ] Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree. [Citation Graph (, )][DBLP ] 3-D floorplanning using labeled tree and dual sequences. [Citation Graph (, )][DBLP ] Multi-voltage floorplan design with optimal voltage assignment. [Citation Graph (, )][DBLP ] Droplet-routing-aware module placement for cross-referencing biochips. [Citation Graph (, )][DBLP ] Physical synthesis of bus matrix for high bandwidth low power on-chip communications. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.004secs